Verilog 應用範例 :LED流水燈  適用於DE2-115 (DE2-70)

源自於 https://hom-wang.gitbooks.io/verilog-hdl/content/Chapter_08.html

程式( 流水燈 )：

module LED_Water( CLK, RST, LED_Out );

    input CLK, RST;
    output [3:0] LED_Out;

    reg    [23:0] Delay_Count = 24'd0;    // USE 50MHz OSC
    reg    [3:0] LED_State = 4'b0001;

    always @( posedge CLK, negedge RST ) begin
        if( !RST ) begin
            Delay_Count <= 24'd0;
            LED_State <= 4'b0001;
        end
        else if( Delay_Count == 24'd25_000_000 ) begin        // 500ms
            Delay_Count <= 24'd0;
            if( LED_State == 4'b0000 )
                LED_State <= 4'b0001;
            else
                LED_State <= LED_State << 1;
        end
        else
            Delay_Count <= Delay_Count + 1'b1;
    end

    assign LED_Out = ~LED_State;

endmodule

//適用於DE2-115
module LED_flow(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );

 LED_Water( CLOCK_50, KEY[0], LEDR[17:0] );


 endmodule

// 程式( 流水燈 )：

module LED_Water( CLK, RST, LED_Out );

    input CLK, RST;
    output [17:0] LED_Out;

    reg    [23:0] Delay_Count = 24'd0;    // USE 50MHz OSC
    reg    [17:0] LED_State = 18'b00_0000_0000_0000_0001;

    always @( posedge CLK, negedge RST ) begin
        if( !RST ) begin
            Delay_Count <= 24'd0;
            LED_State <= 18'b00_0000_0000_0000_0001;
        end
        else if( Delay_Count == 24'd25_000_000 ) begin        // 500ms
            Delay_Count <= 24'd0;
            if( LED_State == 18'b00_0000_0000_0000_0000)
                LED_State <= 18'b00_0000_0000_0000_0001;
            else
                LED_State <= LED_State << 1;
        end
        else
            Delay_Count <= Delay_Count + 1'b1;
    end

    assign LED_Out = ~LED_State;

endmodule