數位IC設計入門-Verilog Sequential logic Serial in Parallel Out Shift register Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog Sequential logic
Serial in Parallel Out Shift register  Behavioral Modeling (& Test Bench)

//=====================================================
//數位IC設計入門-Verilog Sequential logic
//Serial in Parallel Out Shift register  Behavioral Modeling (& Test Bench)

//File Name：SIPO_Shift_Register.v
module SIPO_Shift_Register(clock, clear, in, out);
input clock, clear, in;
output [3:0] out;
reg [3:0] out;

always @(negedge clock)
begin
      if (clear)
      begin
            out = 4'd0;
      end
        
      else
      begin
            out[3] = out[2];
            out[2] = out[1];
            out[1] = out[0];
            out[0] = in;
      end
end

endmodule

//=====================================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
 //module SIPO_Shift_Register(clock, clear, in, out);
 //input clock, clear, in;
 //output [3:0] out;

// Inputs
reg clock=0, clear=1, in=0;

// Outputs
wire [3:0]out;


// Instantiate the Unit Under Test (UUT)
// SIPO_Shift_Register(clock, clear, in, out);

SIPO_Shift_Register UUT(clock, clear, in, out);

initial begin
  $monitor(clock, clear, in, out);
  // Initialize Inputs
  #5 clear=0;
  #15 in=1;
  #10 in=0;
  #15 in=1;
  #10 in=0;
  #15 in=1;
  #15 in=1;
  #10 in=0;
  #5  in=1;
  #15 in=0;
  #10 in=0;
  #15 in=1;
  #10 in=0;
  #15 in=1;
  #15 in=1;
  #10 in=0;
  #5  in=1;
  #15 in=0;
  
  end

always #11 clock= ~clock;  

initial
begin
  #250;   // 模擬終止時間  250 ns
  $stop;
end

endmodule

//=====================================================