數位IC設計入門-Verilog Sequential logic Down Counter 下數計數器MOD10 Behavioral

數位IC設計入門-Verilog 
Sequential  logic   Down Counter 下數計數器MOD10  Behavioral 

//==================================================
//數位IC設計入門-Verilog 
//Sequential  logic   Down Counter 下數計數器MOD10  Behavioral Modeling (& Test Bench)

//File Name：Down_Counter.v
module DOWN_MOD10 (clock, reset, out);
input clock, reset;
output [3:0] out;
reg [3:0] out;

always @(posedge clock)
begin
      if(reset)
      begin
            out = 4'd9;
      end

      else if(out == 4'd0)
      begin
            out = 4'd9;
      end

      else
      begin
            out = out - 1'd1;
      end
end

endmodule

//==================================================

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps    

module Test_bench;

 //module DOWN_MOD10 (clock, reset, out);

 //input clock, reset;

 //output [3:0] out;

 

// Inputs

 reg clock=0, reset=1;

// Outputs

wire [3:0]out;

// Instantiate the Unit Under Test (UUT)

// DOWN_MOD10 (clock, reset, out);

DOWN_MOD10 UUT (clock, reset, out);

initial begin

  $monitor(clock, reset, out);

  // Initialize Inputs

  #5 reset=0;

end

always #10 clock = ~clock;  

initial

begin

  #250;   // 模擬終止時間  250 ns

  $stop;

end

endmodule

//==================================================