數位IC設計入門-Verilog combinational logic 半加器 Behavioral Modeling （Test Bench） 

QuartUS II 91sp2 需設定

//數位IC設計入門-Verilog combinational logic 半加器 Behavioral Modeling （Test Bench） 

module HA(a, b, sum, cy);
  input a, b;
  output sum, cy;
  reg sum, cy;

  always@(a or b)
  begin
        {cy, sum} = a + b;
  end

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
  //module Half_Adder(a, b, sum, cy);
  //input a, b;
  //output sum, carry;

// Inputs
reg a=0,b=0;

// Outputs
wire sum,cy;

// Instantiate the Unit Under Test (UUT)
//module Half_Adder(a, b, sum, cy);

HA UUT(a, b, sum, cy);

initial begin
 $monitor(a, b, sum, cy);
    // Initialize Inputs
 #25 a=1;b=0;
 #25 a=0;b=1;
 #25 a=1;b=1;
end

initial
begin
  #100;   // 模擬終止時間  400 ns
  $stop;
end
endmodule