數位IC設計入門-Verilog combinational logic Half subtractor 半減器 Behavioral Modeling (& Test Bench）

數位IC設計入門-Verilog combinational logic 
Half subtractor 半減器 Behavioral Modeling  (& Test Bench）

 module HS (a, b, difference, borrow);
  input a, b;
  output difference, borrow;
  reg difference, borrow;

  always@(a or b)
  begin
        {borrow, difference} = a - b;
  end

 endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
  //module HS (a, b, difference, borrow);
  //input a, b;
  //output difference, borrow;

// Inputs
reg a=0 ,b=0;

// Outputs
wire difference, borrow;

// Instantiate the Unit Under Test (UUT)
//module HS (a, b, difference, borrow);

HS UUT(a, b, difference, borrow);

initial begin
 $monitor(a, b, difference, borrow);
    // Initialize Inputs
 #25 a=0 ; b=1 ;
 #25 a=1 ; b=0 ;
 #25 a=1 ; b=1 ;

end

initial
begin
  #100;   // 模擬終止時間  100 ns
  $stop;
end


endmodule