數位IC設計入門-Verilog 行為模型(Behavioral Model): AND_OR_Gate

數位IC設計入門-Verilog
行為模型(Behavioral Model): AND_OR_Gate

//需 Import  pin assignments  DE2_115_pin_assignments

module EX3_3(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );
 // blank unused 7-segment digits
assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

assign LEDR=SW;

and_or_behavioral (SW[3:0],LEDG[0]);

endmodule


module and_or_behavioral (in,out);
input  [3:0]in;  // 4位元輸入
output reg out;  // 一位元輸出

always @(in)
begin
out= (in[0] | in[1]) & (in[2] | in[3]);   
end
endmodule