數位IC設計入門-Verilog Sequential logic Parallel in Serial Out Shift register Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog Sequential logic
Parallel in Serial Out Shift register  Behavioral Modeling (& Test Bench)

//=====================================================
//數位IC設計入門-Verilog Sequential logic
//Parallel in Serial Out Shift register  Behavioral Modeling (& Test Bench)
//File Name：PISO_Shift_Register.v
module PISO_Shift_Register(clock, clear, load, in, out);
input clock, clear, load;
input [3:0] in;
output out;
reg [3:0] register;

always @(posedge clock)
begin
      if (clear)
      begin
            register = 4'd0;
      end

      else if (load)
      begin
            register = in;
      end
      
  else
      begin
            register[3] = register[2];
            register[2] = register[1];
            register[1] = register[0];
            register[0] = 1'd0;
      end
end
  
assign out = register[3];

endmodule

//=====================================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
 //PISO_Shift_Register(clock, clear, load, in, out);
 //input clock, clear, load;
 //input [3:0] in;
 //output out;

// Inputs
reg clock=0, clear=1, load=0;
reg [3:0]in=4'b1110;

// Outputs
wire out;


// Instantiate the Unit Under Test (UUT)
// PISO_Shift_Register(clock, clear, load, in, out);

PISO_Shift_Register UUT(clock, clear, load, in, out);

initial begin
  $monitor(clock, clear, load, in, out);
  // Initialize Inputs
  #5  clear=0; load=1;in=4'b0110;
  #5  load=0;
  #50 load=1; in=4'b1110;
  #5  load=0;
  #50 load=1;in=4'b0101;
  #5  load=0;
  #50 load=1;in=4'b0101;
  #5  load=0;
  
  end

always #6 clock= ~clock;  

initial
begin
  #200;   // 模擬終止時間  200 ns
  $stop;
end



endmodule