數位IC設計入門-Verilog Sequential logic Accumlator 累加器 Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog 
Sequential  logic  Accumlator 累加器 Behavioral Modeling (& Test Bench)

//數位IC設計入門-Verilog 
//Sequential  logic  Accumlator 累加器 Behavioral Modeling (& Test Bench)

//File Name：Accumulator.v
module ACC (clock, reset, in, out);
input clock, reset;
input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @(posedge clock)
begin
      if(reset)
      begin
            out = 4'd0;
      end
      
      else
      begin
            out = out + in;
      end
end
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
//module ACC (clock, reset, in, out);
//input clock, reset;
//input [3:0] in;
//output [3:0] out;

// Inputs
reg clock=0, reset=1;
reg [3:0] in;

// Outputs
wire [3:0] out;


// Instantiate the Unit Under Test (UUT)
// ACC (clock, reset, in, out); 

ACC UUT(clock, reset, in, out); 

initial begin
 $monitor(clock, reset, in, out);

 // Initialize Inputs
 #20 in=4'd10; reset=0;
 #20 in=4'd2;
 #20 in=4'd12;
 #20 in=4'd5; 
end

always #10 clock = ~clock;  

initial
begin
  #100;   // 模擬終止時間  100 ns
  $stop;
end



endmodule