Verilog HDL Program for Johnson Counter

Verilog HDL Program for Johnson Counter (10bits)

//declare the Verilog module - The inputs and output port names.
module johnson_cnt_10(clock,reset,q);
   input clock;
   input reset;
   output [9:0] q;

   reg[9:0] a;

    always @(posedge clock)
      if (reset)
        a = 10'b0000000001;

      else
        begin
        a <=  a<<1; // Notice the blocking assignment
        a[0]<=a[9];
        end

    assign q = a;

  endmodule


// 時間單位 1ns, 時間精確度10ps
`timescale 1ns / 1ps
module Test_bench;
// Inputs
reg clock;
reg reset;
// Outputs
    wire[9:0] q;
// Instantiate the Unit Under Test (UUT)
johnson_cnt_10 UUT (
      .clock(clock), 
      .reset(reset), 
      .q(q)
);

  always #10 clock = ~clock;

initial begin
// Initialize Inputs
    clock = 0; 
reset = 0;

#5 reset = 1;
#20 reset = 0;
#300 $finish;
    end 

initial begin
          $monitor($time, " clock=%1b,reset=%1b,q=%4b",clock,reset,q);
end

endmodule