Clock Divider by 1000000

Clock Divider by 1000000

module clock_divide_n(clock_in,clock_out);
input clock_in; // input clock on FPGA
output clock_out; // output clock after dividing the input clock by divisor
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd1000000;
// The frequency of the output clk_out
//  = The frequency of the input clk_in divided by DIVISOR
// For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
// You will modify the DIVISOR parameter value to 28'd50.000.000
// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
always @(posedge clock_in)
begin
counter <= counter + 28'd1;
if(counter>=(DIVISOR-1))
counter <= 28'd0;
end

assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;

endmodule

// 時間單位 1ns, 時間精確度10ps
`timescale 1ns / 1ps
module Test_bench;
 reg  clock_in;
 wire clock_out;

clock_divide_n UUT (
   .clock_in(clock_in),
   .clock_out(clock_out)
);

 initial begin
  // Initialize Inputs
  clock_in = 0;
  // create input clock 2MHz
  forever #250 clock_in = ~clock_in;
 end
endmodule