Clock divide by 4

Clock divide by 4

module clock_divide_4 (input clk,input rst_n,output reg o_clk);

 reg [1:0] cnt;

always@(posedge clk or negedge rst_n) begin

   if (!rst_n)

     cnt <= 0;

   else if (cnt == 3) // 0 ~ 3

     cnt <= 0;

   else

     cnt <= cnt + 1;

 end

always@(posedge clk or negedge rst_n) begin

   if (!rst_n)

     o_clk <= 0;

   else if (cnt < 2) // 0 ~ 1

     o_clk = 0;

   else              // 2 ~ 3

     o_clk = 1;   

 end

endmodule

`timescale 1ns/10ps
module Test_bench;
 reg clk;
 reg rst_n;
 wire o_clk;

clock_divide_4 UUT (
   .clk(clk),
   .rst_n(rst_n),
   .o_clk(o_clk)
 );

 initial begin
   clk   = 1'b1;
   rst_n = 1'b1;
 end

 // 50MHz clk
 always #10 clk = ~clk;
endmodule