8 bits Counters and their use in clock dividers

8 bits Counters and their use in clock dividers 

https://www.realdigital.org/doc/9c21eab4a0f85c50486858a87380d1f6

module Clock_Dividers(
    input clk, rst,
    output reg [7:0] counterout
    );
   
 always @ (posedge(clk), posedge(rst))
 begin
     if (rst) counterout <= 0;
     else counterout <= counterout + 1;
end
endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps    

module Test_bench;

// Inputs

reg clk ; //輸入的訊號

reg rst ; //rst=1 , 0開始count

// Outputs

wire [7:0] counterout; //除過的訊號輸出

// Instantiate the Unit Under Test (UUT)

//module Clock_Dividers(

//    input clk, rst,

//    output reg [7:0] counterout

Clock_Dividers  UUT (

  .clk(clk), //輸入的訊號

  .rst(rst), //reset, 0開始count

  .counterout(counterout) //除過的訊號輸出

  );

   initial begin

    $monitor(clk,rst,counterout);

    // Initialize Inputs

    clk <= 1'b0;

    rst <= 1'b0;

    #4000 $finish();

   end

    always #10 clk=~clk;

endmodule