Clock divide by 100_100_100

Clock divide by  100_100_100 

module clock_divide_100_100_100(clk_in,clk_out1,clk_out2,clk_out3);
input clk_in; // input clock on FPGA
output clk_out1,clk_out2,clk_out3; // output clock after dividing the input clock by divisor
wire   clk_out1,clk_out2,clk_out3;

clock_divide_100 U1(.clock_in(clk_in),.clock_out(clk_out1));
clock_divide_100 U2(.clock_in(clk_out1),.clock_out(clk_out2));
clock_divide_100 U3(.clock_in(clk_out2),.clock_out(clk_out3));

endmodule



module clock_divide_100(clock_in,clock_out);
input clock_in; // input clock on FPGA
output clock_out; // output clock after dividing the input clock by divisor
reg[6:0] counter=7'd0;
parameter DIVISOR = 7'd100;
// The frequency of the output clk_out
//  = The frequency of the input clk_in divided by DIVISOR
// For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
// You will modify the DIVISOR parameter value to 28'd50.000.000
// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
always @(posedge clock_in)
begin
counter <= counter + 7'd1;
if(counter>=(DIVISOR-1))
counter <= 7'd0;
end

assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;

endmodule