verilog 74LS83 4bit Adder

verilog 74LS83 4bit Adder

module adder_74ls83(A, B, C0 ,S,C4);
    output [3:0] S;
    output C4;
    input [3:0] A;
    input [3:0] B;
    input C0;

    assign #10 {C4,S} = A + B + C0;


endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps     

module Test_bench;

reg [3:0] A;

reg [3:0] B;

reg      C0;

 

wire [3:0] S;

wire      C4;

 

adder_74ls83 UUT(

.A(A),

.B(B),

.C0(C0),

.S(S),

.C4(C4)

);

 

initial begin

A  = 4'h0;

B  = 4'h0;

C0 = 4'h0;

$monitor(A,B,C0,S,C4);

#160; C0 = 4'h1;

end

always #20  A = A + 3;

always #40  B = A + 2;

initial begin

      #320 $finish();

end

endmodule