Verilog 4Bits Adder gate level

Verilog 4Bits Adder gate level 

源自於
https://www.cnblogs.com/oomusou/archive/2008/07/11/verilog_4_bit_full_adder.html

module Adder_4bit_gatelevel(
   input  [3:0] a,
   input  [3:0] b,
   input        ci,
   output [3:0] s,
   output       co
 );

wire [2:0] carry;

function fa_s(input a, input b, input ci);
fa_s = a ^ b ^ ci;
endfunction

function fa_co(input a, input b, input ci);
fa_co = a & ci | a & b | b & ci;
endfunction

assign s[0]     = fa_s (a[0], b[0], ci);
assign carry[0] = fa_co(a[0], b[0], ci);

assign s[1]     = fa_s (a[1], b[1], carry[0]);
assign carry[1] = fa_co(a[1], b[1], carry[0]);

assign s[2]     = fa_s (a[2], b[2], carry[1]);
assign carry[2] = fa_co(a[2], b[2], carry[1]);

assign s[3]     = fa_s (a[3], b[3], carry[2]);
assign co       = fa_co(a[3], b[3], carry[2]);

endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module Test_bench;
reg [3:0] a;
reg [3:0] b;
reg      ci;

wire [3:0] s;
wire      co;

Adder_4bit_gatelevel UUT(
.a(a),
.b(b),
.ci(ci),
.s(s),
.co(co)
);

initial begin
a  = 4'h0;
b  = 4'h0;
ci = 4'h0;
$monitor(a,b,ci,s,co);
#160; ci = 4'h1;
end

always #20  a = a + 1;
always #40 b = a + 2;


initial begin
      #320 $finish();
end
endmodule