Verilog 應用範例 :除頻器  適用於DE2-115 (DE2-70)

程式( 除頻器 50MHz to 1kHz )：

module Freq_Divider( CLK, RST, CLK_Out ); /* 除頻器 Use 50MHz OSC */

    // 除頻設定  1kHz 1ms
    Parameter    Div  = 16'd50_000;  // 除頻數(Even)
    parameter    Div2 = 16'd25_000;  // Div/2
    parameter    DivW = 16;          // Divide寬度

    input   CLK, RST;
    output  CLK_Out;
    reg     rCLK_Out;
    reg     [DivW-1:0] CLK_Cnt = 0;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            CLK_Cnt <= 0;
        else if( CLK_Cnt == Div-1 )
            CLK_Cnt <= 0;
        else
            CLK_Cnt <= CLK_Cnt + 1'b1;
    end
    always @( posedge CLK or negedge RST ) begin
        if( !RST )
            CLK_Out <= 0;
        else if( CLK_Cnt <= Div2-1 )
            CLK_Out = 0;
        else
            CLK_Out = 1'b1;
    end

endmodule

//適用於DE2-115 
module MHz50_1KHz(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );
 
 wire FD0,FD1,FD2; 
 Freq_Divider( CLOCK_50, KEY[0], FD0 );  //1KHZ
 
 divide_by_50 u1(FD1,FD0,KEY[0]);  //20HZ
 
 divide_by_50 u2(FD2,FD1,KEY[0]);  //0.4HZ
 
 assign LEDG[0]=FD0; //for debug
 assign LEDG[2]=FD1; //for debug
 assign LEDG[4]=FD2; //for debug

 endmodule

//程式( 除頻器 50MHz to 1kHz )：

module Freq_Divider( CLK, RST, CLK_Out ); /* 除頻器 Use 50MHz OSC */

    // 除頻設定  1kHz 1ms
    
    parameter    Div  = 16'd50_000;  // 除頻數(Even)
    parameter    Div2 = 16'd25_000;  // Div/2
    parameter    DivW = 16;          // Divide寬度

    input   CLK, RST;
    output  CLK_Out;
    reg     CLK_Out;
    reg     [DivW-1:0] CLK_Cnt = 0;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            CLK_Cnt <= 0;
        else if( CLK_Cnt == Div-1 )
            CLK_Cnt <= 0;
        else
            CLK_Cnt <= CLK_Cnt + 1'b1;
    end
    always @( posedge CLK or negedge RST ) begin
        if( !RST )
            CLK_Out <= 0;
        else if( CLK_Cnt <= Div2-1 )
            CLK_Out = 0;
        else
            CLK_Out = 1'b1;
    end

endmodule

module divide_by_50(Q,CLK,RST); input CLK, RST; output Q; reg Q; reg [4:0] count; always @ (posedge CLK or negedge RST) begin if (~RST) begin Q <= 1'b0; count <= 5'b00000; end else if (count < 24) begin count <= count+1'b1; end else begin count <= 5'b00000; Q <= ~Q; end end endmodule