數位IC設計入門-Verilog Sequential logic D Latch 閂鎖器 Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog 
Sequential  logic D Latch 閂鎖器 Behavioral Modeling (& Test Bench)

//數位IC設計入門-Verilog 
//Sequential  logic D Latch 閂鎖器 Behavioral Modeling (& Test Bench)
//File Name：D_Latch.v

module D_LATCH(G, D, Q);   //D:Enable
input G, D;
output Q;
reg Q;

always@(G or D)
begin
    if(G)
        Q = D;
    else
        Q = Q;
end
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
//module D_LATCH (G, D, Q);   //D:Enable
//input G, D;
//output Q;

// Inputs
reg D=0, G=1;

// Outputs
wire Q;


// Instantiate the Unit Under Test (UUT)
// D_LATCH (G, D, Q);   //D:Enable

D_LATCH UUT(G, D, Q);   //D:Enable

initial begin
 $monitor(G, D, Q);

    // Initialize Inputs
 //#20 select[3:0]=4'd0 ; a=8'd0 ; b=8'd0;
 #20 D=1 ;  G=1; 
 #20 D=0 ;  G=0; 
 #20 D=0 ;  G=1; 
 #20 D=1 ;  G=0; 

end

initial
begin
  #100;   // 模擬終止時間  100 ns
  $stop;
end



endmodule