DE2-115 基本邏輯閘實驗(1) and nand or nor xor xnor gate

DE2-115 基本邏輯閘實驗 (Verilog 硬體描述語言實務)

需 Import  pin assignments  DE2_115_pin_assignments

//=============================================
//gate level basic gate and nad or nor xor xnor
//=============================================
module ch4_1_1_p4_2(SW, LEDR, LEDG , CLOCK_50 ,KEY
                     ,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 ,HEX5 ,HEX6 ,HEX7 );

input  [17:0] SW;   // toggle switches
input  [3:0] KEY;       // Push bottom
input  CLOCK_50;   //Clock 27MHz , 50Mhz

output [17:0] LEDR;   // red  LEDS
output [8:0] LEDG;   // green LEDs
 
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 ; //7-segment display
assign HEX0=7'b111_1111; //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;  //off 7-segment Display
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

assign A=SW[1]; //and
assign B=SW[0];

assign C=SW[3]; //nand
assign D=SW[2];

assign E=SW[5]; //or
assign F=SW[4];

assign G=SW[7]; //nor
assign H=SW[6];

assign I=SW[9]; //xor
assign J=SW[8];

assign K=SW[11]; //xnor
assign L=SW[10];

and  (Oand , A, B);
nand (Onand, C, D);
or   (Oor,   E, F);
nor  (Onor,  G, H);
xor  (Oxor,  I, J);
xnor (Oxnor, K, L);

assign LEDR[0] = Oand;
assign LEDR[2] = Onand;
assign LEDR[4] = Oor;
assign LEDR[6] = Onor;
assign LEDR[8] = Oxor;
assign LEDR[10]= Oxnor;

endmodule