alex9ufo 聰明人求知心切: 1月 2020

2020年1月31日星期五

DE2-115 16x4 Priority Encoder

DE2-115 16x4 Priority Encoder

//需 Import pin assignments DE2_115_pin_assignments

module Encoder_if(
//input CLOCK_50, // 50 MHz clock
//input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
//output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
// inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
/*
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
*/
);

// All inout port turn to tri-state
//assign GPIO_0 = 36'hzzzzzzzzz;
//assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
//assign LCD_ON = 1'b1;
//assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
//assign HEX4 = 7'b111_1111;
//assign HEX5 = 7'b111_1111;
//assign HEX6 = 7'b111_1111;
//assign HEX7 = 7'b111_1111;

assign LEDR=SW;
M_encoder( LEDG[3:0],SW[15:0],SW[17] );

endmodule

//-----------------------------------------------------
// Design Name : encoder_using_if
// File Name : encoder_using_if.v
// Function : Encoder using If
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module M_encoder(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in[1]==1'b1) begin
binary_out = 1;
end if (encoder_in[2] == 1'b1) begin
binary_out = 2;
end if (encoder_in[3] == 1'b1) begin
binary_out = 3;
end if (encoder_in[4] == 1'b1) begin
binary_out = 4;
end if (encoder_in[5] == 1'b1) begin
binary_out = 5;
end if (encoder_in[6] == 1'b1) begin
binary_out = 6;
end if (encoder_in[7] == 1'b1) begin
binary_out = 7;
end if (encoder_in[8] == 1'b1) begin
binary_out = 8;
end if (encoder_in[9] == 1'b1) begin
binary_out = 9;
end if (encoder_in[10] == 1'b1) begin
binary_out = 10;
end if (encoder_in[11] == 1'b1) begin
binary_out = 11;
end if (encoder_in[12] == 1'b1) begin
binary_out = 12;
end if (encoder_in[13] == 1'b1) begin
binary_out = 13;
end if (encoder_in[14] == 1'b1) begin
binary_out = 14;
end if (encoder_in[15] == 1'b1) begin
binary_out = 15;
end
end
end

endmodule

https://www.youtube.com/watch?v=P5yuUIx2W-c

Design 8x3 Priority Encoder in Verilog Coding and Verify with TestBench

源自於 https://vlsicoding.blogspot.com/2013/10/design-3x8-priority-encoder-in-verilog.html

Priority Encoder allocates priority to each input. Design and Test Bench code of 8x3 Priority Encoder is given below. Output are set according to priorities of inputs. So if input with higher priority is present then inputs with lower priorities are ignored and generates output according to highest priority input.

S. No.	Name	Direction	Width	Remark
1.	D_in	IN	8 bit	Input lines
3.	D_out	OUT	3 bit	Output lines

Design Code

module prio_enco_8x3(d_out, d_in);

   output [2:0] d_out;
   input [7:0] d_in ;

assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:
               (d_in[6] ==1'b1 ) ? 3'b110:
               (d_in[5] ==1'b1 ) ? 3'b101:
               (d_in[4] ==1'b1) ? 3'b100:
               (d_in[3] ==1'b1) ? 3'b011:
               (d_in[2] ==1'b1) ? 3'b010:
               (d_in[1] ==1'b1) ? 3'b001:
               (d_in[0] ==1'b1) ? 3'b000: 3'bxxx;

endmodule

Above code is synthesized by Xilinx Vivado and RTL view of Priority Encoder is shown below.

RTL view of Priority Encoder

Test Bench Code

`timescale 1ns/1ps
module prio_enco_8x3_tst;
   reg [7:0] d_in;
   wire[2:0] d_out;

   prio_enco_8x3 u1 (.d_out(d_out), .d_in(d_in) );

   initial
     begin
    d_in=8'b11001100;
    #10;
    d_in=8'b01100110;
    #10;
    d_in=8'b00110011; 
    #10;
    d_in=8'b00010010;
    #10;
    d_in=8'b00001001;
    #10;
    d_in=8'b00000100;
    #10;
    d_in=8'b00000011;
    #10;
    d_in=8'b00000001;
    #10;
    d_in=8'b00000000;
    # 10; 
    $stop;
     end // initial begin
 endmodule

Above design code is simulated using given Test Bench code by Xilinx Vivado and Simulated waveform is shown below.

Waveform of Priority Encoder

DE2-115 16x4 Encoder

DE2-115 16x4 Encoder

SW[15:0] Encoder input 只能SW[15:0]一個輸入
SW[17] enable
LEDG[3:0] Encoder output

//需 Import pin assignments DE2_115_pin_assignments

module encoder_using_if(
//input CLOCK_50, // 50 MHz clock
//input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
//output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
// inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
/*
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
*/
);

// All inout port turn to tri-state
//assign GPIO_0 = 36'hzzzzzzzzz;
//assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
//assign LCD_ON = 1'b1;
//assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
//assign HEX4 = 7'b111_1111;
//assign HEX5 = 7'b111_1111;
//assign HEX6 = 7'b111_1111;
//assign HEX7 = 7'b111_1111;

assign LEDR=SW;
M_encoder( LEDG[3:0],SW[15:0],SW[17] );

endmodule

//-----------------------------------------------------
// Design Name : encoder_using_if
// File Name : encoder_using_if.v
// Function : Encoder using If
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module M_encoder(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end

endmodule

https://www.youtube.com/watch?v=3uE6hrteVJE

DE2-115 Verilog encoder_using_if

  1 //-----------------------------------------------------
  2 // Design Name : encoder_using_if
  3 // File Name   : encoder_using_if.v
  4 // Function    : Encoder using If
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module encoder_using_if(
  8 binary_out , //  4 bit binary output
  9 encoder_in , //  16-bit input
 10 enable       //  Enable for the encoder
 11 ); 
 12 //-----------Output Ports---------------
 13 output [3:0] binary_out  ;
 14 //-----------Input Ports---------------
 15 input  enable ; 
 16 input [15:0] encoder_in ; 
 17 //------------Internal Variables--------
 18 reg [3:0] binary_out ;  
 19 //-------------Code Start-----------------
 20 always @ (enable or encoder_in)
 21  begin 
 22    binary_out = 0; 
 23    if (enable) begin
 24      if (encoder_in == 16'h0002) begin
 25       binary_out = 1;
 26      end  if (encoder_in == 16'h0004) begin 
 27       binary_out = 2; 
 28      end  if (encoder_in == 16'h0008) begin 
 29       binary_out = 3; 
 30      end  if (encoder_in == 16'h0010) begin 
 31       binary_out = 4; 
 32      end  if (encoder_in == 16'h0020) begin 
 33       binary_out = 5; 
 34      end  if (encoder_in == 16'h0040) begin 
 35       binary_out = 6; 
 36      end  if (encoder_in == 16'h0080) begin 
 37       binary_out = 7; 
 38      end  if (encoder_in == 16'h0100) begin 
 39       binary_out = 8; 
 40      end  if (encoder_in == 16'h0200) begin 
 41       binary_out = 9; 
 42      end if (encoder_in == 16'h0400) begin 
 43       binary_out = 10; 
 44      end  if (encoder_in == 16'h0800) begin 
 45       binary_out = 11; 
 46      end  if (encoder_in == 16'h1000) begin
 47       binary_out = 12; 
 48      end  if (encoder_in == 16'h2000) begin 
 49       binary_out = 13;
 50      end  if (encoder_in == 16'h4000) begin 
 51       binary_out = 14; 
 52      end if (encoder_in == 16'h8000) begin 
 53       binary_out = 15; 
 54      end
 55   end
 56 end
 57       
 58 endmodule

You could download file encoder_using_if.v here

Verilog Examples

Verilog Examples

源自於 http://www.asic-world.com/examples/verilog/index.html

Decoder And Encoders

Mux

Flip Flop And Latches

Counters

Memories

Parity And CRC

Modeling With Switch Primitives

Modeling With Gate Primitives

User Defined Primitives

PLI Examples

Verilog UART Model

Verilog Arbiter Model

DE2-115 運算子之使用 (資料流層敘述)

DE2-115 運算子之使用 (資料流層敘述)

//需 Import pin assignments DE2_115_pin_assignments

// Ch05 op.v
// 運算子之使用 (資料流層敘述)

/*
module op (A, B, Ci, Co, S, X, Y, Z);
input [3:0] A, B; // A, B 四位元輸入
input Ci; // Ci 一位元輸入
output Co; // Co 一位元輸出
output [3:0] S, X, Y, Z; // S, X, Y, Z 四位元輸出

assign {Co, S} = A + B + Ci; // 全加法
assign X = {A[2:0], A[3]}; // A 循環左移 1 位元
assign Y = B ~^ 4'b1010; // B 和四位元資料1010作互斥反或
assign Z = (~A) & B; // A’B

endmodule
*/
//=====================================================
//需 Import pin assignments DE2_115_pin_assignments
//=====================================================
module Operator(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
);

// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
// blank unused 7-segment digits
assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

wire [3:0]A,B,S, X,Y,Z;
wire Ci,Co;

assign A=SW[3:0]; // A, B 四位元輸入
assign B=SW[7:4]; // A, B 四位元輸入
assign Ci=SW[8]; // Ci 一位元輸入
assign LEDG[4]=Co; // Co 一位元輸出
assign LEDG[3:0]=S;

assign LEDR[3:0]= X ; // S, X, Y, Z 四位元輸出
assign LEDR[7:4]= Y ; // S, X, Y, Z 四位元輸出
assign LEDR[11:8]= Z ; // S, X, Y, Z 四位元輸出

assign {Co, S} = A + B + Ci; // 全加法
assign X = {A[2:0], A[3]}; // A 循環左移 1 位元
assign Y = B ~^ 4'b1010; // B 和四位元資料1010作互斥反或
assign Z = (~A)&B; // A’B

endmodule

HDL tutorials

HDL tutorials

源自於 https://www.fpga4fun.com/HDLtutorials.html

HDL languages are nowadays the preferred way to create FPGA designs. The most commonly used HDL languages are Verilog and VHDL. This site showns examples in Verilog, but VHDL could have been used, as they are equivalent for most purposes.

For an in-depth discussion, take a look to VHDL & Verilog Compared & Contrasted (PDF).

Here are a few tutorials:

Verilog

A Verilog tutorial from Deepak Kumar Tala.
A Verilog HDL quick reference guide from Sutherland HDL, Inc.
A Verilog HDL quick reference card from Qualis Design corp.
An Handbook on Verilog HDL from Bucknell University. It focuses on behavioral Verilog though, so useful for simulation or verification only.
A self-study course for learning Verilog.

VHDL

A VHDL Tutorial from Green Mountain Computing Systems, Inc.
A VHDL quick reference card from Qualis Design corp.
The Accolade VHDL Reference Guide includes a language overview and several examples.
The VHDL-Online pages.
A VHDL-Handbook from Hardi Electronics.
The VHDL Math Tricks of the Trade from Synthworks.

DE2-115 7-segments LED displays

DE2-115 7-segments LED displays

參考來源 https://www.fpga4fun.com/Opto3.html

//需 Import pin assignments DE2_115_pin_assignments

//============================================
//The 7-segments display
//============================================
/*
module LED_7seg(
input clk,
output segA, segB, segC, segD, segE, segF, segG, segDP
);

// cnt is used as a prescaler
reg [23:0] cnt;
always @(posedge clk) cnt <= cnt+24'h1;
wire cntovf = &cnt;

// BCD is a counter that counts from 0 to 9
reg [3:0] BCD;
always @(posedge clk) if(cntovf) BCD <= (BCD==4'h9 ? 4'h0 : BCD+4'h1);

reg [7:0] SevenSeg;
always @(*)
case(BCD)
4'h0: SevenSeg = 8'b11111100;
4'h1: SevenSeg = 8'b01100000;
4'h2: SevenSeg = 8'b11011010;
4'h3: SevenSeg = 8'b11110010;
4'h4: SevenSeg = 8'b01100110;
4'h5: SevenSeg = 8'b10110110;
4'h6: SevenSeg = 8'b10111110;
4'h7: SevenSeg = 8'b11100000;
4'h8: SevenSeg = 8'b11111110;
4'h9: SevenSeg = 8'b11110110;
default: SevenSeg = 8'b00000000;
endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg;
endmodule

module LED_7seg(
input clk,
output segA, segB, segC, segD, segE, segF, segG, segDP
);

reg [23:0] cnt;
always @(posedge clk) cnt <= cnt+24'h1;
wire cntovf = &cnt;

reg [3:0] BCD_new, BCD_old;
always @(posedge clk) if(cntovf) BCD_new <= (BCD_new==4'h9 ? 4'h0 : BCD_new+4'h1);
always @(posedge clk) if(cntovf) BCD_old <= BCD_new;

reg [4:0] PWM;
wire [3:0] PWM_input = cnt[22:19];
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;
wire [3:0] BCD = (cnt[23] | PWM[4]) ? BCD_new : BCD_old;

reg [7:0] SevenSeg;
always @(*)
case(BCD)
4'h0: SevenSeg = 8'b11111100;
4'h1: SevenSeg = 8'b01100000;
4'h2: SevenSeg = 8'b11011010;
4'h3: SevenSeg = 8'b11110010;
4'h4: SevenSeg = 8'b01100110;
4'h5: SevenSeg = 8'b10110110;
4'h6: SevenSeg = 8'b10111110;
4'h7: SevenSeg = 8'b11100000;
4'h8: SevenSeg = 8'b11111110;
4'h9: SevenSeg = 8'b11110110;
default: SevenSeg = 8'b00000000;
endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg;
endmodule
*/
//============================================
//需 Import pin assignments DE2_115_pin_assignments
module LED_7seg(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
);

// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

wire [7:0] segout0; //HEX 0
wire [7:0] segout3; //HEX 1

// cnt is used as a prescaler
reg [23:0] cnt;
always @(posedge CLOCK_50) cnt <= cnt+24'h1;
wire cntovf = &cnt;

// BCD is a counter that counts from 0 to 9
reg [3:0] BCD;
always @(posedge CLOCK_50) if(cntovf) BCD <= (BCD==4'h9 ? 4'h0 : BCD+4'h1);

//====================================================
//Finally let's try a "smooth" counter (fades each digit into then next).
//====================================================
reg [26:0] cnt1;
always @(posedge CLOCK_50) cnt1 <= cnt1+30'h1;
wire cntovf1 = &cnt1;

reg [3:0] BCD_new, BCD_old;
always @(posedge CLOCK_50) if(cntovf1) BCD_new <= (BCD_new==4'h9 ? 4'h0 : BCD_new+4'h1);
always @(posedge CLOCK_50) if(cntovf1) BCD_old <= BCD_new;

reg [4:0] PWM;
wire [3:0] PWM_input = cnt1[26:23];
always @(posedge CLOCK_50) PWM <= PWM[3:0]+PWM_input;
wire [3:0] BCD1 = (cnt1[26] | PWM[4]) ? BCD_new : BCD_old;

_7seg UUT0(.hex((BCD[3:0])),.seg(segout0));
_7seg UUT3(.hex((BCD1[3:0])),.seg(segout3));
assign HEX0=segout0[6:0];
assign HEX3=segout3[6:0];

endmodule

//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;

// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end

endmodule

https://www.youtube.com/watch?v=1QpwIz_R2JM

DE2-115 Varying an LED intensity ( LED on off ,LED half-lit , Fine-tuning LED intensity)

DE2-115 Varying an LED intensity

參考來源 https://www.fpga4fun.com/Opto2.html

PWM_input=SW[3:0] 控制LED的亮度

//需 Import pin assignments DE2_115_pin_assignments

//==============================================
/*
//Turning an LED on and off
module LEDblink(clk, LED);
input clk; // clock typically from 10MHz to 50MHz
output LED;

// create a binary counter
reg [31:0] cnt;
always @(posedge clk) cnt <= cnt+1;

assign LED = cnt[22]; // blink the LED at a few Hz (using the 23th bit of the counter, use a different bit to modify the blinking rate)
endmodule

//Making an LED half-lit
module LEDhalflit(clk, LED);
input clk; // clk should be at least 200Hz.
// Anything above is fine (most FPGA boards have adequate clocks, running at a few 10's of MHz)
output LED;

reg toggle;
always @(posedge clk) toggle <= ~toggle; // toggles at half the clk frequency (at least 100Hz)

assign LED = toggle;
endmodule

//Fine-tuning the LED intensity

module LED_PWM(clk, PWM_input, LED);
input clk;
input [3:0] PWM_input; // 16 intensity levels
output LED;

reg [4:0] PWM;
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];
endmodule
*/

//需 Import pin assignments DE2_115_pin_assignments
module LED_onoff_halflit(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
);

// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

// create a binary counter
reg [31:0] cnt;
always @(posedge CLOCK_50) cnt <= cnt+1;

//Turning an LED on and off
assign LEDG[0] = cnt[25]; // blink the LED at a few Hz (using the 23th bit of the counter, use a different bit to modify the blinking rate)

//-----------------------------------------------
//Making an LED half-lit
reg toggle;
always @(posedge CLOCK_50) toggle <= ~toggle; // toggles at half the clk frequency (at least 100Hz)
assign LEDG[1] = toggle;
//-----------------------------------------------
//Fine-tuning the LED intensity
wire [3:0] PWM_input; // 16 intensity levels
assign PWM_input=SW[3:0];

reg [4:0] PWM;
always @(posedge CLOCK_50) PWM <= PWM[3:0]+PWM_input;

assign LEDG[2] = PWM[4];
endmodule

https://www.youtube.com/watch?v=00Yucb7bbwY

DE2-115 LED glow

DE2-115 LED glow

參考來源 https://www.fpga4fun.com/Opto0.html

//=============================
//This makes the LED "glow".
// Note: Use a "clk" clock signal at around 20MHz.
//Otherwise the effect might be too slow or too fast to be appreciated.
//=============================
//需 Import pin assignments DE2_115_pin_assignments

/*
module LED_glow(clk, LED);
input clk;
output LED;

reg [23:0] cnt;
always @(posedge clk) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];
reg [4:0] PWM;
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];
endmodule */

module LED_glow(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
);

// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;

// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;

// blank unused 7-segment digits
assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

reg [23:0] cnt;
always @(posedge CLOCK_50) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];
reg [4:0] PWM;

always @(posedge CLOCK_50) PWM <= PWM[3:0]+PWM_input;

assign LEDG[0] = PWM[4];

endmodule

https://www.youtube.com/watch?v=ZHWjItEWkjM

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