alex9ufo 聰明人求知心切

2020年4月22日星期三

Non-blocking Procedural Assignment in Verilog

Non-blocking Procedural Assignment in Verilog

//--------------------------------------------------
//4-bit register for Non-blocking Procedural Assignment
//--------------------------------------------------
module Nonblocking( CLK, RESET, Din,Qout);
input CLK, RESET;
input Din;
output reg [3:0] Qout;

always @ (posedge CLK or posedge RESET)
//Positive edge CLK and asynchronous RESET
if (RESET)
Qout <= 4'b0000;
else
begin
Qout[0] <= Din;
Qout[1] <= Qout[0];
Qout[2] <= Qout[1];
Qout[3] <= Qout[2];
end
endmodule

//======================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps

module TB;

module Nonblocking( CLK, RESET, Din,Qout);

input CLK, RESET;

input Din;

output reg [3:0] Qout;

// Inputs

reg CLK;

reg RESET;

reg Din;

// Outputs

wire [3:0] Qout;

// Instantiate the UUT

Nonblocking UUT (

.Qout(Qout),

.CLK(CLK),

.RESET(RESET),

.Din(Din)

);

initial

$monitor ($time, "Data in=%b, CLK=%b, RESET=%b, Qout=%b", Din, CLK, RESET, Qout);

initial //Initialize input signals

begin

CLK = 0;

RESET = 1;

Din = 0;

end

initial

begin

#35 RESET=0; //Disable RESET at 35 ns

#50 Din = 1; //Set Din at different times

#100 Din = 0;

#75 Din = 1;

end

always #10 CLK=~CLK; //Set clock with a period 20 ns

initial #300 $finish; //Complete simulation after 400 ns

endmodule

Blocking Procedural Assignment in Verilog

//--------------------------------------------------

//4-bit register for Blocking Procedural Assignment

//--------------------------------------------------

module Blocking( CLK, RESET, Din,Qout);

input CLK, RESET;

input Din;

output reg [3:0] Qout;

always @ (posedge CLK or posedge RESET)

//Positive edge CLK and asynchronous RESET

if (RESET)

Qout = 4'b0000;

else

begin

Qout[0] = Din;

Qout[1] = Qout[0];

Qout[2] = Qout[1];

Qout[3] = Qout[2];

end

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps

module TB;

module Blocking( CLK, RESET, Din,Qout);

input CLK, RESET;

input Din;

// Inputs

reg CLK;

reg RESET;

reg Din;

// Outputs

wire [3:0] Qout;

// Instantiate the UUT

Blocking UUT (

.Qout(Qout),

.CLK(CLK),

.RESET(RESET),

.Din(Din)

);

initial

$monitor ($time, "Data in=%b, CLK=%b, RESET=%b, Qout=%b", Din, CLK, RESET, Qout);

initial //Initialize input signals

begin

CLK = 0;

RESET = 1;

Din = 0;

end

initial

begin

#35 RESET=0; //Disable RESET at 35 ns

#50 Din = 1; //Set Din at different times

#150 Din = 0;

#75 Din = 1;

end

always #20 CLK=~CLK; //Set clock with a period 20 ns

initial #400 $finish; //Complete simulation after 400 ns

endmodule

源自於 https://jk3527101.pixnet.net/blog/post/14108608

Blocking & Non Blocking

1. Blocking的語法 = //循序式的方式執行程式

Exp :

always@(posedge clock)

begin

Data = A&B; // blocking會先執行第一行程式

OUT = A+B; // 緊接著再執行第二行程式

end

注意 : 電路都使用blocking的方式設計會造成電路串連的太長，導致延遲太多時間。

2. Non blocking的語法 <= //平行式的方式執行程式

Exp :

always@(posedge clock)

begin

Data <= A&B; // non blocking會同時執行

OUT <= A+B; //

end

注意 : 電路都使用non blocking的方式設計會造成電路面積加大(成本提高)，因為並行處理的輸出都要額外給予一個暫存器來儲存。

對於新手而言，該如何準確的判斷哪些時候該選用blocking，哪些時候又該選用non blocking來做處理，有相當程度的困難。因此通常會給予新手一些建議，避免設計電路上的錯誤。

1. 組合邏輯assign電路採用blocking，且必須搭配wire。

2. 循序邏輯always電路採用non blocking，且必須搭配reg。

# 組合邏輯à與時間無關，大多作為運算用。(如加、減法器)

# 循序邏輯à與時間有關，大多作為記憶資料，但不能運算。(如正反器)

8-bit synchronous counter wit asynchronous reset

8-bit synchronous counter wit asynchronous reset

Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

An example of this is given as.

3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
and so on..

The Modulo number can be increased by adding more flip-flops to the counter and cascading is a method of achieving higher modulus counters. Then the modulo or MOD number can simply be written as: MOD number = 2n

4-bit Modulo-16 Counter

Multi-bit asynchronous counters connected in this manner are also called “Ripple Counters” or ripple dividers because the change of state at each stage appears to “ripple” itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency.

//--------------------------------------------------

// 8-bit synchronous counter wit asynchronous reset

//--------------------------------------------------

module CNT_8bit(CLK, RESET, COUNT);

input CLK;

input RESET;

output [7:0] COUNT;

reg [7:0] COUNT;

always @(posedge CLK or posedge RESET)

begin

if (RESET)

COUNT <= 8'b0;

else

COUNT <= COUNT + 1;

end

endmodule

//=====================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps

module TB;

module CNT_8bit(CLK, RESET, COUNT);

input CLK;

input RESET;

output [7:0] COUNT;

// Inputs

reg CLK;

reg RESET;

// Outputs

wire [7:0] COUNT;

// Bidirs

initial

$monitor($time, " COUNT = %d RESET = %b", COUNT[7:0], RESET);

// Instantiate the UUT

CNT_8bit uut (

.CLK(CLK),

.RESET(RESET),

.COUNT(COUNT)

);

// Stimulate the RESET signal

initial begin

RESET = 1'b1;

#45 RESET = 1'b0;

#200 RESET = 1'b1;

#50 RESET = 1'b0;

end

// Set up the clock to toggle every 100 time units

initial begin

CLK = 1'b0;

forever #10 CLK=~CLK;

end

//Finish the simulation at time 400

initial begin

#6400 $finish;

end

endmodule

JK Flip Flop in Verilog

JK Flip Flop in Verilog

module JK_FF (j,k,clk,q);
input j,k,clk;
output reg q;

always @ (posedge clk)
case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 0;
2'b10 : q <= 1;
2'b11 : q <= ~q;
endcase

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
reg j,k,clk=1'b0;
wire q;

JK_FF UUT ( .j(j),
.k(k),
.clk(clk),
.q(q));
always #5 clk = ~clk;

initial begin
j <= 1;
k <= 0;

#7 j <= 0;
k <= 0;
#27 j <= 0;
k <= 1;
#27 j <= 1;
k <= 1;
#20 $stop;
end

initial
$monitor ("j=%0d k=%0d q=%0d", j, k, q);
endmodule

Info: ModelSim-Altera Info: # run -all
Info: ModelSim-Altera Info: # j=1 k=0 q=x
Info: ModelSim-Altera Info: # j=1 k=0 q=0
Info: ModelSim-Altera Info: # j=1 k=0 q=1
Info: ModelSim-Altera Info: # j=0 k=0 q=1
Info: ModelSim-Altera Info: # j=0 k=1 q=1
Info: ModelSim-Altera Info: # j=0 k=1 q=0
Info: ModelSim-Altera Info: # j=1 k=1 q=0
Info: ModelSim-Altera Info: # j=1 k=1 q=1
Info: ModelSim-Altera Info: # j=1 k=1 q=0

Verilog Positive Edge Detector

module pos_edge_det (sig,clk,pe);

input sig;
// Input signal for which positive edge has to be detected
input clk;
// Input signal for clock
output pe;
// Output signal that gives a pulse when a positive edge occurs

reg sig_dly;
// Internal signal to store the delayed version of signal

// This always block ensures that sig_dly is exactly 1 clock behind sig
always @ (posedge clk) begin
sig_dly <= sig;
end

// Combinational logic where sig is AND with delayed, inverted version of sig
// Assign statement assigns the evaluated expression in the RHS to the internal net pe
assign pe = sig & ~sig_dly;

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
reg sig; // Declare internal TB signal called sig to drive the sig pin of the design
reg clk; // Declare internal TB signal called clk to drive clock to the design

// Instantiate the design in TB and connect with signals in TB
pos_edge_det UUT(
.sig(sig),
.clk(clk),
.pe(pe));

// Generate a clock of 100MHz
always #5 clk = ~clk;

// Drive stimulus to the design
initial begin
clk <= 0;
sig <= 0;
#15 sig <= 1;
#20 sig <= 0;
#15 sig <= 1;
#10 sig <= 0;
#20
$stop;
end
endmodule

Verilog Tutorial Contents

Verilog Positive Edge Detector

源自於 https://www.chipverify.com/verilog/verilog-positive-edge-detector

Design

The idea behind a positive edge detector is to delay the original signal by one clock cycle, take its inverse and perform a logical AND with the original signal.

 
module pos_edge_det ( input sig,            // Input signal for which positive edge has to be detected
                      input clk,            // Input signal for clock
                      output pe);           // Output signal that gives a pulse when a positive edge occurs
 
    reg   sig_dly;                          // Internal signal to store the delayed version of signal
 
    // This always block ensures that sig_dly is exactly 1 clock behind sig
  always @ (posedge clk) begin
    sig_dly <= sig;
  end
 
    // Combinational logic where sig is AND with delayed, inverted version of sig
    // Assign statement assigns the evaluated expression in the RHS to the internal net pe
  assign pe = sig & ~sig_dly;            
endmodule

The module shown above is named pos_edge_det and has two inputs and one output. The design aims to detect the positive edge of input sig, and output pe. So we expect to see a pulse on pe whenever sig changes from value 0 to 1.

We create an internal signal called sig_dly of type reg that can store a single clock cycle delayed version of sig, and is achieved by the always block. Output pe is an implicit variable of type wire and can be assigned only by a continous assignment. Hence we have used the assign statement to assign an expression to pe. The expression simply takes sig and does a logical AND with the inversion of sig.

Testbench

In order to simulate our design, we have to place the module of our verilog code inside a testbench. The testbench simply holds our design and provides us a way to send in signals as inputs and observe the outputs to make sure that it operates as required.

 
module tb;
  reg sig;         // Declare internal TB signal called sig to drive the sig pin of the design
  reg clk;         // Declare internal TB signal called clk to drive clock to the design
 
  // Instantiate the design in TB and connect with signals in TB
  pos_edge_det ped0 (  .sig(sig),           
               .clk(clk),
                  .pe(pe));
 
  // Generate a clock of 100MHz
  always #5 clk = ~clk;           
 
  // Drive stimulus to the design
  initial begin
    clk <= 0;
    sig <= 0;
    #15 sig <= 1;
    #20 sig <= 0;
    #15 sig <= 1;
    #10 sig <= 0;
    #20 $finish;
  end  
endmodule

Clock for our design is generated by the always block which toggles clk every 5 time units, there by generating a clock with period = 10 time units. Basic design stimulus is written within the initial block which makes the simulator advance in time and drive the design with specific values appropriately.

Hardware Schematic

The behavioral model in Verilog was synthesized using Xilinx Vivado FPGA design tool and the hardware schematic has been generated as shown below. It can be seen that the one clock delay is implemented using a DFF and the output of the flip flop is wired to the input of an AND gate through an inverter. These digital elements are substituted with logical cells that belong to a real cell library for a given technology node.

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2020年4月22日 星期三

4-bit Modulo-16 Counter

Verilog Positive Edge Detector

Verilog Positive Edge Detector

Design

Testbench

Hardware Schematic

2020年4月22日星期三