使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Divide_by_50M to 1Hz為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Divide_by_50M to 1Hz為例(FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
//1 HZ CLOCK GENERATOR
//module Clock_1Hz(clk, reset, clk_1Hz);
//input clk, reset;
//output clk_1Hz;
 wire CLK1hz1 , CLK1hz2 ;
 Clock_1Hz(CLOCK_50,KEY[0],CLK1hz1);
 assign LEDG[0]=CLK1hz1;
 
 //module Divide_by_50M_counter(clr,clk,clk_1Hz);
 // input clr,clk;
 // output clk_1Hz;
 Divide_by_50M_counter(CLOCK_50,KEY[0],CLK1hz2);
 assign LEDG[2]=CLK1hz2;
 
endmodule

//1 HZ CLOCK GENERATOR
//The goal of this always procedural block is to generate 1Hz clock from a
//50MHz clock that is used in the Altera FPGA board.
module Divide_by_50M_counter(clk,clr,clk_1Hz);
input clr,clk;
output clk_1Hz;
reg clk_1Hz =1'b0;

integer counter_50M =0;
always @(posedge clk,  negedge clr)
begin
 if (!clr)
counter_50M <=0;
 else if (counter_50M <25000000)
 begin
counter_50M <= counter_50M + 1;
 end
 else if (counter_50M ==25000000)
 begin
clk_1Hz <= !clk_1Hz;
counter_50M <=0;
 end
end
endmodule