HBLbits_Verilog Basic_Hadd
Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.
module top_module(
input a, b,
output cout, sum );
assign {cout,sum}= a+b;
//assign cout = a & b;
//assign sum = a ^ b;
endmodule
input a, b,
output cout, sum );
assign {cout,sum}= a+b;
//assign cout = a & b;
//assign sum = a ^ b;
endmodule
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