2021年4月22日 星期四

HBLbits_Verilog Basic_Exams/m2014 q4e

HBLbits_Verilog Basic_Exams/m2014 q4e 

Implement the following circuit:

Exams m2014q4e.png


module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~(in1 | in2);
endmodule

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