HBLbits_Verilog Basic_Exams/ece241 2013 q2
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.
Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.
f(a,b,c,d)=Σ (2,7,15) + d(3,8,11,12)
2_variables 3_variables 4_variables 5_variables 6_variables
Logic circuit simplification (SOP and POS)
This is an online Karnaugh map generator that makes a kmap, shows you how to group the terms,
shows the simplified Boolean equation, and draws the circuit for up to 6 variables.
It also handles Don't cares.
The Quine-McCluskey solver can be used for up to 6 variables if you prefer that.
Select the number of variables, then choose SOP (Sum of Products) or POS (Product of Sums)
or Quine-McCluskey, and try some calculations. SOP is the default.
This logic simplification application is not intended for design purposes. It is just for fun.
It is just a programming project for me.
I enjoyed writing the software and hopefully you will enjoy using it.
I have tried to be sure that it is accurate but I can not guarantee it.
So, if you plan to use the output for any purpose, you must confirm it yourself.
PRODUCT of SUMS : y = (C) (B' + D) (A' + B)
SUM of PRODUCTS ： y = CD + A'B'C
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
//y = CD + A'B'C
assign out_sop= (c&d) | (~a & ~b &c);
// y = (C) (B' + D) (A' + B)
assign out_pos = (c) & (~b | d ) & (~a | b);
endmodule
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