Verilog Provides in-built primitives for basic gate and switch level modeling. Any circuit can be modeled by using continuous assignment of gate and switch level primitives.
and (strong1, weak0)#(1,2) gate1(out, in1, in2);Basic Gates
and
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0
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1
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x
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z
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or
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0
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1
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x
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z
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xor
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0
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1
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x
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z
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0
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0
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0
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0
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0
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0
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0
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1
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x
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x
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0
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0
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1
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x
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x
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1
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0
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1
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x
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x
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1
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1
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1
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1
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1
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1
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1
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0
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x
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x
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x
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0
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x
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x
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x
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x
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x
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1
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x
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x
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x
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x
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x
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x
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x
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z
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0
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x
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x
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x
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z
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x
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1
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x
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x
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z
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x
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x
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x
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x
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nand
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0
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1
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x
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z
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nor
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0
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1
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x
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z
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xnor
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0
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1
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x
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z
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0
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1
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1
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1
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1
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0
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1
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0
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x
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x
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0
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1
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0
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x
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x
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1
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1
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0
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x
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x
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1
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0
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0
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0
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0
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1
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0
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1
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x
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x
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x
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1
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x
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x
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x
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x
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x
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0
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x
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x
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x
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x
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x
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x
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x
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z
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1
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x
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x
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x
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z
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x
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0
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x
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x
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z
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x
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x
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x
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x
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buf
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not
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input
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output
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input
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output
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0
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0
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0
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1
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1
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1
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1
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0
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x
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x
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x
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x
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z
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x
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z
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x
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bufif1, bufif0, notif1, notif0 Gates
bufif0
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control input
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bufif1
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control input
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0
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1
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x
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z
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0
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1
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x
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z
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data
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0
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0
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z
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L
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L
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data
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0
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z
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0
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L
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L
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input
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1
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1
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z
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H
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H
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input
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1
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z
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1
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H
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H
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x
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x
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z
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x
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x
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x
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z
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x
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x
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x
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z
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x
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z
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x
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x
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z
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z
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x
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x
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x
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notif0
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control input
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notif1
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control input
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0
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1
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x
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z
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0
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1
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x
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z
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data
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0
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1
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z
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H
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H
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data
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0
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z
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1
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H
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H
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input
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1
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0
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z
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L
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L
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input
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1
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z
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0
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L
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L
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x
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x
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z
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x
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x
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x
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z
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x
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x
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x
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z
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x
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z
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x
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x
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z
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z
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x
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x
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x
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nmos, pmos, rnmos, rpmos, cmos, and rcmos switches
The cmos and rcmos switches have four ports: the first is an output port, the second is a data port, the third is a n-control port, and the fourth a is p-control port.
pmos
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control input
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nmos
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control input
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rpmos
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0
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1
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x
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z
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rnmos
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0
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1
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x
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Z
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data
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0
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0
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z
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L
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L
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data
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0
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z
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0
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L
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L
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input
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1
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1
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z
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H
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H
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input
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1
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z
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1
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H
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H
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x
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x
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z
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x
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x
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x
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z
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x
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x
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x
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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cmos
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N control
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rcmos
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0
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1
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x
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z
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P control
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0
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1
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x
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z
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0
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1
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x
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z
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0
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1
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x
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z
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0
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1
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x
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z
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Data
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0
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0
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z
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L
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L
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0
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0
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0
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0
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0
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L
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L
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L
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0
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L
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L
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L
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1
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1
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z
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H
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H
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1
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1
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1
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1
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1
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H
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H
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H
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1
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H
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H
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H
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x
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x
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z
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x
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x
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x
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x
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x
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x
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x
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x
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x
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x
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x
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x
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x
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x
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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z
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Symbols L and H have a special meaning. The symbol L means that the output has 0 or z value. The symbol H means that the output has 1 or z value. Any transition to H or L is treated as a transition to x.
rtranif0, rtranif1, tranif0 and tranif1 switches
The rtranif0, rtranif1, tranif0 and tranif1 switches have three ports: two bidirectional data ports and one control port (third position on port list).
tran and rtran switches
The tran and rtran switches have two bidirectional data ports.
pullup and pulldown sources
The instantiation pullup and pulldown sources cannot contain delay declaration. The pullup can contain only strength1 specification (the strength0 declaration is optional). The pulldown can contain only strength0 specification (the strength1 declaration is optional).
The pullup source places a logic value 1 on connected signals. The pull down source places a logic value 0 on connected signals.
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