A Simple Design and-or-invert (AOI) gate in Verilog.

A Simple Design

 and-or-invert (AOI) gate in Verilog.

Verilog: an AOI gate module

// Verilog code for AND-OR-INVERT gate

module AOI (input A, B, C, D, output F);

  assign F = ~((A & B) | (C & D));

endmodule

// end of Verilog code

Comments

// Verilog code for AND-OR-INVERT gate

Module and Port declarations

module AOI (input A, B, C, D, output F);

A port may correspond to a pin on an IC, an edge connector on a board, or any logical channel of communication with a block of hardware. The port declarations include the names of the ports ( e.g., A, B ), and the direction that information is allowed to flow through the ports (input, output or inout).

Endmodule

endmodule

The module definition is terminated by the Verilog keyword endmodule.

Functionality

assign F = ~((A & B) | (C & D));

// end of Verilog code

Verilog 1995

The above example is written using Verilog-2001 syntax. 

Many people continue to use the 1995 syntax, which is still allowed in Verilog-2001. In Verilog-1995 the module header would look like this:

module AOI (A, B, C, D, F);
  input A, B, C, D;
  output F;