Overview of Verilog HDL

Overview of Verilog HDL

/* A simple AND gate 
File: and.v              */

module andgate (a, b, y);
input a, b;
output y;

assign y = a & b;

endmodule

/* testbench for AND gate 
File: and_tb.v */

module andgate_tb;
wire t_y;
reg t_a, t_b;

andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );

initial
begin

$monitor(t_a, t_b, t_y);

t_a = 1'b0;
t_b = 1'b0;

#5
t_a = 1'b0;
t_b = 1'b1;

#5 
t_a = 1'b1;
t_b = 1'b0;

#5
t_a = 1'b1;
t_b = 1'b1;

end
endmodule















Integer
Meaning
Stored as
5'b00101
5 bit binary 00101
00101
8'b0
8 bit binary 00000000
00000000
8'b101
8 bit binary 00000101
00000101
8'd5
8 bit decimal 5
00000101
8'h9f
8 bit hex 9f
10011111
3'd1
3 bit decimal 1
001
4'bz
3 bit decimal z
zzzz
4'bx1
binary
xxx1
5'b11z
binary
0011z
15
32 bit decimal 15
0....01111(32 bits)
'o5
32 bit octal 5
0....00101(32 bits)




Rules:


1: Active high bit


0: Active low bit


z: high impedance


x: Uncertain/ Don't care


If not mentioned, length is 32 bit and data type is integer by default.


If value is larger than the length, left most bits will be truncated


If value is smaller,


0's are filled to the left if left most bit is 0 or 1


'z' are filled if left most bit is z


'x' are filled if left most bit is x