Verilog Loop Statements

Verilog Loop Statements

There are 4 types of looping stetements in Verilog:

forever statement;

repeat(expression) statement;

while(expression) statement;

for(initial_assignment; expression; step_assignment) statement;

forever Loop:

initial 

begin 
   clk = 0; 
   forever #5 clk = ~clk; 
end 

repeat Loop:

initial 

begin 
  x = 0; 
  repeat( 16 ) 
  begin 
     #2 $display("y= ", y); 
     x = x + 1; 
  end 
end 

while Loop:

initial 

begin 
  x = 0; 
  while( x <= 10 ) 
  begin 
     #2 $display("y= ", y); 
     x = x + 1; 
  end 
end 

for Loop:

for(initial_assignment; expression; step_assignment) statement;

Syntax is similar to C language except that begin--end is used instead of {--} to combine more than one statements. Remember that we don't have ++ operator in Verilog.

for( i = 0; i <= 10; i++ )
   mem[i] = 0;