王國華 老師的 數位系統導論

http://cad6.csie.fju.edu.tw/digital99/experiment.htm   王國華 老師

實 驗 課 進 度 表

　

週次	日期	實驗名稱	預定進度	教材	學期分數 比例	書面 繳交期限
1	2/14, 2/18	Lab 0: Logic Schematic	Introduction of Quartus II Design Flow Using Schematic	Design Entry using Schematic	8%	(乙)，(甲)
2	2/21, 2/25	Lab 0: Verilog Tutorial	Design Flow Using Verilog Hardware Description Language	Design Entry Using Verilog		3/1 , 3/4
3	2/28, 3/4	Lab 1:  四位元加/減法器 (1/3)	Half-Adder, Full-Adder, 4-bit Adder Component Design Using Current Design Bus Design 4-bit Adder Component Design and Functional Simulation	製作元件 BUS範例-四位元加法器	13%
4	3/7,3/11	Lab 1:  四位元加/減法器 (2/3)	4-bit Adder/Subtractor & its Functional Simulation Top-Level Logic Circuit  Download of 4-bit Adder/Subtractor (Schematic)	4-bit Adder/Subtractor
				如何匯入外部元件
				seg7.v
				4-bit Adder/Sub上層設定
				如何匯入Pin_Assignment
				DE2-70 896
				DE2 672
5	3/14,3/18	Lab 1:  四位元加/減法器 (3/3)	Download of 4-bit Adder/Subtractor (Verilog)	4-bit Adder/SubtractorTop		3/21，3/25
6	3/21,3/25	Lab 2:  八位元比較器 (1/2)	1-bit, 2-bit, 4-bit , and 8-bit Comparators (Schematic) Functional Simulation of All Components Download of 8-bit Comparator (Schematic)	8-bit Comparators8-bit Comparators TOP	10%
7	3/28, 4/1	Lab 2:  八位元比較器( 2/2)	1-bit, 2-bit, 4-bit Comparators (Verilog) Functional Simulation of All Components Download of 8-bit Comparator (Verilog)	8-bit Comparator (Verilog)		4/ 7，4/8
8	4/4, 4/8	Lab 3:  四位元乘法器 (1/2)	Download of 4-bit Multiplier (Verilog using Structural & Dataflow Modeling)	Array-Multiplier-partMultiplier Top	12%
9	4/11, 4/15	Lab 3:  四位元乘法器 (2/2)	Download of 4-bit Multiplier (Verilog using generate statements)	nbit-Multiplier-Generate		4/18，4/22
10	4/18,4/22	期中上機考 (1)	期中上機考 (1)	甲班考題 甲班補考 乙班考題 乙班考題解答	12%
11	4/25,4/29	期中上機考 (2)	期中上機考 (2)	甲班考題04/29 乙班考題 乙班補考 乙班補考 04/28
12	5/2,5/6	Lab 4: Simulation of Flop-Flops	Functional Simulation of JK, D, and T Flip-Flops	Flip-Flops	6%
13	5/9,5/13	Lab 5:  Sequence Counter	Design of Sequence Counter using Verilog Functional Simulation of Sequence Counter (Verilog)Download of Sequence Counter	Sequence Counter-二乙	6%
14	5/16,5/20	Lab 6:  Analysis of Sequential Circuit	Functional Simulation of Sequential Circuits	Analysis of Sequential CircuitsLibrary Parameter Modules Using LPMs	6%
15	5/23,5/27	Lab 7:  One's Bit Counter (1/2)	Design of Control Unit and Datapath Veilog Code of One's Bit Counter Functional Simulation of One's Bit Counter	One's Bit Counter	12%
16	5/30,6/3	Lab 7:  One's Bit Counter (2/2)	Download of One's Bit Counter
17	6/6,6/10	Lab 8:  Multiplier (1/2)	Design of Control Unit and Datapath Veilog Code of Multiplier Functional Simulation of  Multiplier	Multiplier	15%
18	6/13,6/17	Lab 8:  Multiplier (2/2)	Download of Multiplier	甲班小考下載
期末專題 (Optional)	6/20	Divider	Design of Control Unit and Datapath Veilog Code of Divider Functional Simulation of  Divider Download of Enhance Divider	Divider	12%