Verilog 有限狀態機( Finite State Machine )

源自於 https://hom-wang.gitbooks.io/verilog-hdl/content/Chapter_07.html

 

程式( FSM )：

module Finite_State_Machine( CLK, RST, State );

    parameter   State_A = 2'b00, State_B = 2'b01,
                State_C = 2'b10, State_D = 2'b11;

    input   CLK, RST;
    output  [1:0] State;
    reg     [1:0] State;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            State = State_A;
        else
            case( State )
                State_A:    State <= State_B;
                State_B:    State <= State_D;
                State_C:    State <= State_A;
                State_D:    State <= State_C;
                default:    State <= State_A;
            endcase
    end

endmodule

//========================================
//Finite_State_Machine
//有限狀態機( Finite State Machine )
module FSM( CLK, RST, State );

    parameter   State_A = 2'b00, State_B = 2'b01,
                State_C = 2'b10, State_D = 2'b11;

    input   CLK, RST;
    output  [1:0] State;
    reg     [1:0] State;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            State = State_A;
        else
            case( State )
                State_A:    State <= State_B;
                State_B:    State <= State_D;
                State_C:    State <= State_A;
                State_D:    State <= State_C;
                default:    State <= State_A;
            endcase
    end

endmodule
//========================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;

    parameter   State_A = 2'b00, State_B = 2'b01,
                State_C = 2'b10, State_D = 2'b11;

 //   input   CLK, RST;
 //   output  [1:0] reg State;

 // Inputs
 reg CLK, RST;

 // Outputs
 wire [1:0]State;

//Finite_State_Machine
//有限狀態機( Finite State Machine )

// Instantiate the Unit Under Test (UUT)
FSM DUT(
.CLK(CLK),
.RST(RST),
.State(State)
);


 initial begin
  $monitor( CLK, RST, State );
 // Initialize Inputs
 CLK = 0;
 RST = 1;
 fork
#250 RST = 0;
#350 RST = 1;
#600  $stop;
 join
end

always #20 CLK = !CLK;
 

endmodule

//========================================