Verilog 3x8 解碼器( Decoder )

參考來源 https://hom-wang.gitbooks.io/verilog-hdl/content/Chapter_07.html

程式( 3 to 8解碼器)：

module DeCoder( In, Out );

    input   [2:0] In;
    output  [7:0] Out;

    wire    [2:0] In;
    reg     [7:0] Out;

    always @( In ) begin
        case( In )
            3'b000:     Out <= 8'b0000_0001;
            3'b001:     Out <= 8'b0000_0010;
            3'b010:     Out <= 8'b0000_0100;
            3'b011:     Out <= 8'b0000_1000;
            3'b100:     Out <= 8'b0001_0000;
            3'b101:     Out <= 8'b0010_0000;
            3'b110:     Out <= 8'b0100_0000;
            3'b111:     Out <= 8'b1000_0000;
            default:    Out <= 8'bxxxx_xxxx;
        endcase
    end

endmodule

//=====================================

module Decoder_3x8( In, Out );

    input   [2:0] In;
    output  [7:0] Out;

    wire    [2:0] In;
    reg     [7:0] Out;

    always @( In ) begin
        case( In )
            3'b000:     Out <= 8'b0000_0001;
            3'b001:     Out <= 8'b0000_0010;
            3'b010:     Out <= 8'b0000_0100;
            3'b011:     Out <= 8'b0000_1000;
            3'b100:     Out <= 8'b0001_0000;
            3'b101:     Out <= 8'b0010_0000;
            3'b110:     Out <= 8'b0100_0000;
            3'b111:     Out <= 8'b1000_0000;
            default:    Out <= 8'bzzzz_zzzz;
        endcase
    end

endmodule

//=====================================
// 時間單位 100ns, 時間精確度10 ps
`timescale 100ns/10ps
module Test_bench;
//    input   [2:0] In;
//    output  [7:0] Out;

    
wire [7:0] Out; 
reg  [2:0] In=3'b000;


 Decoder_3x8 DUT( .In(In), .Out(Out) );

// initial程序結構區塊, 產生輸入信號波形
initial begin

$monitor(In, Out );
 
 #100;    // 100ns
 In=3'b001 ; 

 #100;    // 200ns
 In=3'b010 ; 
 
 #100;    // 300ns
 In=3'b011 ; 
 
 #100;    // 400ns
 In=3'b100  ; 
 
 #100;    // 500ns
 In=3'b101  ; 
 
 #100;    // 600ns
 In=3'b110 ; 
  
 #100;    // 700ns
 In=3'b111 ; 
 
 #100;    // 700ns
 In=3'b1x1 ; 
 
 end

initial
begin
  #900;   // 模擬終止時間  900 ns
    $stop;
end

endmodule