數位IC設計入門-Verilog combinational logic Adder subtractor 加減器 Behavioral Modeling (& Test Bench)

 數位IC設計入門-Verilog combinational logic 
 Adder  subtractor 加減器 Behavioral Modeling (& Test Bench)


// 數位IC設計入門-Verilog combinational logic 
// Adder  subtractor 加減器 Behavioral Modeling (& Test Bench）
// 選擇select =0 加法  select =1 減法
// 溢位 overflow

  module ADD_SUB(a, b, c , select, out, overflow);
  input [3:0] a, b;
  input     c; 
  input select;
  output [3:0] out;
  output overflow;
  reg [3:0] out;
  reg overflow;

  always@(a or b or select)
  begin
        {overflow, out} = (select) ? (a + b + c ) : (a - b - c);
  end

  endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
  //ADD_SUB(a, b, c,select, out, overflow);
  //input [3:0] a, b;
  //input   c;
  //input select;
  //output [3:0] out;
  //output overflow;

// Inputs
reg [3:0]a=0;
reg [3:0]b=0;
reg c=0;
reg select=0;

// Outputs
wire [3:0]out;
wire overflow;

// Instantiate the Unit Under Test (UUT)
//ADD_SUB(a, b, c,select, out, overflow);

ADD_SUB UUT(a, b,c, select, out, overflow);

initial begin
 $monitor(a, b,c, select, out, overflow);
    // Initialize Inputs
 #25 a[3:0]=4'h0 ; b[3:0]=4'h0 ;c=1; select=0;
 #25 a[3:0]=4'hA ; b[3:0]=4'h9 ;c=0; select=0;
 #25 a[3:0]=4'h5 ; b[3:0]=4'hA ;c=1; select=0;
 #25 a[3:0]=4'h5 ; b[3:0]=4'h8 ;c=0; select=0;
 #25 a[3:0]=4'h2 ; b[3:0]=4'h6 ;c=1; select=0;
 #25 a[3:0]=4'h7 ; b[3:0]=4'hf ;c=0; select=0;
 #25 a[3:0]=4'hf ; b[3:0]=4'hf ;c=1; select=0;

 #25 a[3:0]=4'h0 ; b[3:0]=4'h0 ;c=1; select=1;
 #25 a[3:0]=4'hA ; b[3:0]=4'h9 ;c=0; select=1;
 #25 a[3:0]=4'h5 ; b[3:0]=4'hA ;c=1; select=1;
 #25 a[3:0]=4'h5 ; b[3:0]=4'h8 ;c=0; select=1;
 #25 a[3:0]=4'h2 ; b[3:0]=4'h6 ;c=1; select=1;
 #25 a[3:0]=4'h7 ; b[3:0]=4'hf ;c=0; select=1;
 #25 a[3:0]=4'hf ; b[3:0]=4'hf ;c=1; select=1;

end

initial
begin
  #400;   // 模擬終止時間  400 ns
  $stop;
end


endmodule