//需 Import pin assignments DE2_115_pin_assignments
// Ch10 BCD999_1.v
// 產生 0 ~ 999 計數值
//需 Import pin assignments DE2_115_pin_assignments
module BCD999(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
// inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
/*
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
*/
);
// All inout port turn to tri-state
//assign GPIO_0 = 36'hzzzzzzzzz;
//assign GPIO_1 = 36'hzzzzzzzzz;
// turn LCD ON
//assign LCD_ON = 1'b1;
//assign LCD_BLON = 1'b1;
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
wire [7:0] segout2; //HEX 2
assign LEDR=SW;
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider cdiv(CLOCK_50,KEY[0],myclock);
assign LEDG[0]=myclock[0]; //for debug
wire [11:0] Q1;
BCD999_2(myclock[2],SW[0],Q1);
seg7_lut UUT0(.hex((Q1[3:0])),.seg(segout0));
seg7_lut UUT1(.hex((Q1[7:4])),.seg(segout1));
seg7_lut UUT2(.hex((Q1[11:8])),.seg(segout2));
assign HEX0=segout0[6:0];
assign HEX1=segout1[6:0];
assign HEX2=segout2[6:0];
endmodule
// Ch10 BCD999_2.v
// 產生 0 ~ 999 計數值
module BCD999_2 (Clk,Clr,Q);
input Clk,Clr; // 一位元輸入
output [11:0] Q; // 十二位元輸出
wire Clk1,Clk2,Clk3; // 宣告為連接線資料
// 產生計數值
BCD BCD1 (Clk , Clr, Q[ 3:0], Clk1);
BCD BCD2 (Clk1, Clr, Q[ 7:4], Clk2);
BCD BCD3 (Clk2, Clr, Q[11:8], Clk3);
endmodule
// Ch10 BCD.v
// BCD (mod-10) 計數器
module BCD (Clk_i, Clr, Cnt, Clk_o);
input Clk_i,Clr; // 一位元輸入
output [3:0] Cnt; // 四位元輸出
output Clk_o; // 一位元輸出
reg [3:0] Cnt; // 宣告為暫存器資料
// 除 10 (0 ~ 9)
always@ (posedge Clk_i )
if (Clr || Cnt == 9) // 除 10
Cnt = 0;
else
Cnt = Cnt + 1;
assign Clk_o = ~(Cnt[3] & ~Cnt[2] & ~Cnt[1] & Cnt[0]); // = 9 時
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module seg7_lut(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
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