To Code a Stopwatch in Verilog----適用於DE2-70 的程式

50MHz * 0.1 sec = 5000000 So the clock cycle is repeated 5M times in 0.1 second.
The next step is to calculate the size of the register that will hold this count. 

This is done by using the log formulas. 
Here x is the unknown: 2exp(x) = 5000000 Taking log on both sides: log 2exp(x) = log 5000000 (x) log (2) = log 5000000 x = log 5000000 / log 2 x = 22.3 

Hence a 23 bit wide register will be able to hold a count of 5000000. 
源自於 http://simplefpga.blogspot.co.uk/2012/07/to-code-stopwatch-in-verilog.html

//適用於DE2-70 的程式
module Stop_watch(
 input [17:0]SW,
 input [3:0] KEY,
 input  CLOCK_50,

 output [17:0] LEDR,
 output [7:0] LEDG,
 output [6:0] HEX0,
 output [6:0] HEX1,
 output [6:0] HEX2,
 output [6:0] HEX3,
 output [6:0] HEX4,
 output [6:0] HEX5,
 output [6:0] HEX6,
 output [6:0] HEX7
 );

//assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
//assign HEX2=7'b111_1111;
//assign HEX3=7'b111_1111;
//assign HEX4=7'b111_1111;
//assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
assign LEDR[17:0]=SW[17:0];  //SW status =>LEDR

wire [3:0] digit1,digit2,digit3,digit4,digit5;
wire clk_1hz;

/*module stopwatch(
    input clock,   //clock_50MHz
    input reset,
    input start,   //Enable
    output reg [3:0] d5,d4,d3,d2,d1
    ); */

    
stopwatch u0(CLOCK_50,KEY[0],SW[17],digit5,digit4,digit3,digit2,digit1);

hex_7seg u3(digit1,HEX0);
hex_7seg u4(digit2,HEX2);
hex_7seg u5(digit3,HEX3);
hex_7seg u6(digit4,HEX4);
hex_7seg u7(digit5,HEX5);

endmodule


module stopwatch(
    input clock,   //clock_50MHz
    input reset,
    input start,   //Enable
    output reg [3:0] d5,d4,d3,d2,d1
    );

reg [22:0] ticker; //23 bits needed to count up to 5M bits
wire click;


//the mod 5M clock to generate a tick ever 0.1 second

always @ (posedge clock or negedge reset)
begin
 if(!reset)    //DE2-70 KEY[0]=normal Hi , so pressed down is Low

  ticker <= 0;

 else if(ticker == 5_000_000) //if it reaches the desired max value reset it
  ticker <= 0;
  
 else if(start)             //only start if the input is set high
  ticker <= ticker + 1;
end

assign click = ((ticker == 5_000_000)?1'b1:1'b0); //click to be assigned high every 0.1 second

always @ (posedge clock or negedge reset)
begin
 if (!reset)
  begin
   d1 <= 0;
   d2 <= 0;
   d3 <= 0;
   d4 <= 0;
   d5 <= 0;
   
  end
   
 else if (click) //increment at every click  (0.1Sec)
   begin
   if(d1 == 9) //xxx9 - the 0.1 second digit
      begin  //if_1
      d1 <= 0;
     
    if (d2 == 9) //xx99
       begin  // if_2
       d2 <= 0;
       
       if (d3 == 5) //x599 - the two digit seconds digits
           begin //if_3
           d3 <= 0;
           
           if(d4 == 9) //9599 - The minute digit
              begin //if_4
              d4 <= 0;
             
             if (d5==5) //59599--- The 10's minute digit
                 d5 <= 0;
             else
                 d5=d5+1;
             
             end    // end if-4
             
             else   
              d4 <= d4 + 1;
           end
       else //else_3
        d3 <= d3 + 1;
    end
     
    else //else_2
      d2 <= d2 + 1;
   end
    
   else //else_1
     d1 <= d1 + 1;
  end
end
endmodule
 module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
  4'h0: seg = 7'b1000000;
  4'h1: seg = 7'b1111001;  // ---a----
  4'h2: seg = 7'b0100100;  // |   |
  4'h3: seg = 7'b0110000;  // f   b
  4'h4: seg = 7'b0011001;  // |   |
  4'h5: seg = 7'b0010010;  // ---g----
  4'h6: seg = 7'b0000010;  // |   |
  4'h7: seg = 7'b1111000;  // e   c
  4'h8: seg = 7'b0000000;  // |   |
  4'h9: seg = 7'b0011000;  // ---d----
  4'ha: seg = 7'b0001000;
  4'hb: seg = 7'b0000011;
  4'hc: seg = 7'b1000110;
  4'hd: seg = 7'b0100001;
  4'he: seg = 7'b0000110;
  4'hf: seg = 7'b0001110;
endcase

endmodule