DE2-115 4-digit BCD (0000~9999)

DE2-115 4-digit BCD (0000~9999)

Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.

You may want to instantiate or modify some one-digit decade counters.

設計一個16位的十進制BCD計數器（個位占4位，十位占4位，百位占4位，千位占4位），然後個位進位，十位進位，百位進位時，都輸出一個使能信號。

//Filename:digi_12clock.v
module Countbcd (
 input  CLOCK_50,
 input  [17:0] SW,
 input  [3:0]  KEY,
 output [7:0]  LEDG,
 output [6:0]  HEX0,
 output [6:0]  HEX1,
 output [6:0]  HEX2,
 output [6:0]  HEX3
);
wire  clk_1;
wire [3:0] w_sq0;
wire [3:0] w_sq1;
wire [3:0] w_sq2;
wire [3:0] w_sq3;
// 1Hz clock
//divn # (.WIDTH(26), .N(50_000000))
divn # (.WIDTH(26), .N(10_000000))
u0 (  .clk(CLOCK_50), .rst_n(KEY[0]), .o_clk(clk_1));
top_module u1( 
 .clk(clk_1), 
 .reset(SW[16]), 
 .ena(LEDG[3:0]), 
 .q({w_sq3,w_sq2,w_sq1,w_sq0}) // output  
 ); 
// dig0 to seg7
seg7_lut u2 ( .i_dig(w_sq0), .o_seg(HEX0));
// dig1 to seg7
seg7_lut u3 ( .i_dig(w_sq1), .o_seg(HEX1));
// dig2 to seg7
seg7_lut u4 ( .i_dig(w_sq2), .o_seg(HEX2));
// dig3 to seg7
seg7_lut u5 ( .i_dig(w_sq3), .o_seg(HEX3));
endmodule
//===================================
module top_module ( 
 input clk, 
 input reset, // Synchronous active-high reset
 output [3:1] ena, 
 output [15:0] q); 
 reg [3:0] ones; 
 reg [3:0] tens; 
 reg [3:0] hundreds; 
 reg [3:0] thousands; 
//======================
always@(posedge clk)begin 
    if(reset)begin 
         ones <= 4'd0; 
     end 
     else if(ones == 4'd9)begin 
         ones <= 4'd0; 
     end 
     else begin 
         ones <= ones + 1'b1; 
    end 
end 
//======================
always@(posedge clk)begin 
if(reset)begin 
         tens <= 4'd0; 
       end 
    else if(tens == 4'd9 && ones == 4'd9)begin 
         tens <= 4'd0; 
         end 
    else if(ones == 4'd9) begin 
         tens <= tens + 1'b1; 
         end 
end 
//======================
always@(posedge clk)begin 
if(reset)begin 
        hundreds <= 4'd0; 
      end 
    else if(hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9)begin 
        hundreds <= 4'd0; 
      end 
    else if(tens == 4'd9 && ones == 4'd9) begin 
        hundreds <= hundreds + 1'b1; 
         end 
end 
//======================
 always@(posedge clk)begin 
   if(reset)begin 
thousands <= 4'd0; 
      end 
   else if(thousands == 4'd9 && hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9)begin 
        thousands <= 4'd0; 
        end 
   else if(hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9) begin 
         thousands <= thousands + 1'b1; 
         end 
end 
//======================
assign q = {thousands, hundreds, tens, ones}; 
assign ena[1] = (ones == 4'd9) ? 1'b1 : 1'b0; 
assign ena[2] = (tens == 4'd9 && ones == 4'd9) ? 1'b1 : 1'b0; 
assign ena[3] = (hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9)
? 1'b1:1'b0;   
endmodule
 //===================================
/*
Filename  : divn.v
*/
module divn  (
  input  clk,
  input  rst_n,
  output o_clk
);
parameter WIDTH = 3;
parameter N  = 6;
reg [WIDTH-1:0] cnt_p;
reg [WIDTH-1:0] cnt_n;
reg  clk_p;
reg  clk_n;
assign o_clk = (N == 1) ? clk : (N[0]) ? (clk_p | clk_n) : (clk_p);
always@(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt_p <= 0;
else if (cnt_p == (N-1))
cnt_p <= 0;
else
cnt_p <= cnt_p + 1;
end
always@(posedge clk or negedge rst_n) begin
if (!rst_n)
clk_p <= 1;
else if (cnt_p < (N>>1))
clk_p = 1;
else
clk_p = 0;
end
always@(negedge clk or negedge rst_n) begin
if (!rst_n)
cnt_n <= 0;
else if (cnt_n == (N-1))
cnt_n <= 0;
else
cnt_n <= cnt_n + 1;
end
always@(negedge clk or negedge rst_n) begin
if (!rst_n)
clk_n <= 1;
else if (cnt_n < (N>>1))
clk_n = 1;
else
clk_n = 0;
end
endmodule
//===================================
/*
Filename : seg7_lut.V
*/
module seg7_lut (
input  [3:0] i_dig,
output reg [6:0] o_seg
);
always@(i_dig) begin
case(i_dig)
4'h1: o_seg = 7'b111_1001;  //  ---t----
4'h2: o_seg = 7'b010_0100;  // |        |
4'h3: o_seg = 7'b011_0000;  // lt       rt
4'h4: o_seg = 7'b001_1001;  // |        |
4'h5: o_seg = 7'b001_0010;  //  ---m----
4'h6: o_seg = 7'b000_0010;  // |        |
4'h7: o_seg = 7'b111_1000;  // lb       rb
4'h8: o_seg = 7'b000_0000;  // |        |
4'h9: o_seg = 7'b001_1000;  //  ---b----
4'ha: o_seg = 7'b000_1000;
4'hb: o_seg = 7'b000_0011;
4'hc: o_seg = 7'b100_0110;
4'hd: o_seg = 7'b010_0001;
4'he: o_seg = 7'b000_0110;
4'hf: o_seg = 7'b000_1110;
4'h0: o_seg = 7'b100_0000;
endcase
end
endmodule
//===================================