FPGA designs with Verilog

https://verilogguide.readthedocs.io/en/latest/index.html

Contents:

• 1. First project
  • 1.1. Introduction
  • 1.2. Creating the project
  • 1.3. Digital design using ‘block schematics’
  • 1.4. Manual pin assignment and compilation
  • 1.5. Load the design on FPGA
  • 1.6. Digital design using ‘Verilog codes’
  • 1.7. Pin assignments using ‘.csv’ file
  • 1.8. Converting the Verilog design to symbol
  • 1.9. Convert Block schematic to ‘Verilog code’ and ‘Symbol’
  • 1.10. Conclusion
• 2. Overview
  • 2.1. Introduction
  • 2.2. Modeling styles
    • 2.2.1. Continuous assignment statements
    • 2.2.2. Comparators using Continuous assignment statements
    • 2.2.3. Structural modeling
    • 2.2.4. Procedural assignment statements
    • 2.2.5. Mixed modeling
  • 2.3. Conclusion
• 3. Data types
  • 3.1. Introduction
  • 3.2. Lexical rules
  • 3.3. Data types
  • 3.4. Logic values
  • 3.5. Number representation
  • 3.6. Signed numbers
  • 3.7. Operators
  • 3.8. Arithmetic operator
    • 3.8.1. Bitwise operators
    • 3.8.2. Relational operators
    • 3.8.3. Logical operators
    • 3.8.4. Shift operators
    • 3.8.5. Concatenation and replication operators
    • 3.8.6. Conditional operator
    • 3.8.7. Parameter and localparam
    • 3.8.8. localparam
    • 3.8.9. Parameter and defparam
  • 3.9. Conclusion
• 4. Procedural assignments
  • 4.1. Introduction
  • 4.2. Combinational circuit and sequential circuit
  • 4.3. Concurrent statements and sequential statements
  • 4.4. ‘always’ block
  • 4.5. Blocking and Non-blocking assignment
  • 4.6. Guidelines for using ‘always’ block
    • 4.6.1. ‘always’ block for ‘combinational designs’
    • 4.6.2. ‘always’ block for ‘latched designs’
    • 4.6.3. ‘always’ block for ‘sequential designs’
  • 4.7. If-else statement
  • 4.8. Case statement
  • 4.9. Problem with Loops
  • 4.10. Loop using ‘if’ statement
  • 4.11. Conclusion
• 5. VHDL designs in Verilog
  • 5.1. Introduction
  • 5.2. VHDL designs in Verilog
  • 5.3. Conclusion
• 6. Visual verifications of designs
  • 6.1. Introduction
  • 6.2. Flip flops
    • 6.2.1. D flip flop
    • 6.2.2. D flip flop with Enable port
  • 6.3. Counters
    • 6.3.1. Binary counter
    • 6.3.2. Mod-m counter
  • 6.4. Clock ticks
  • 6.5. Seven segment display
    • 6.5.1. Implementation
    • 6.5.2. Test design for 7 segment display
  • 6.6. Visual verification of Mod-m counter
  • 6.7. Conclusion
• 7. Finite state machine
  • 7.1. Introduction
  • 7.2. Comparison: Mealy and Moore designs
  • 7.3. Example: Rising edge detector
    • 7.3.1. State diagrams: Mealy and Moore design
    • 7.3.2. Implementation
    • 7.3.3. Outputs comparison
    • 7.3.4. Visual verification
  • 7.4. Glitches
    • 7.4.1. Combinational design in asynchronous circuit
    • 7.4.2. Unfixable Glitch
    • 7.4.3. Combinational design in synchronous circuit
  • 7.5. Moore architecture and Verilog templates
    • 7.5.1. Regular machine
    • 7.5.2. Timed machine
    • 7.5.3. Recursive machine
  • 7.6. Mealy architecture and Verilog templates
    • 7.6.1. Regular machine
    • 7.6.2. Timed machine
    • 7.6.3. Recursive machine
  • 7.7. Examples
    • 7.7.1. Regular Machine : Glitch-free Mealy and Moore design
    • 7.7.2. Timed machine: programmable square wave
    • 7.7.3. Recursive Machine : Mod-m counter
  • 7.8. When to use FSM design
  • 7.9. Conclusion
• 8. Design Examples
  • 8.1. Introduction
  • 8.2. Random number generator
    • 8.2.1. Linear feedback shift register (LFSR)
    • 8.2.2. Visual test
  • 8.3. Shift register
    • 8.3.1. Bidirectional shift register
    • 8.3.2. Parallel to serial converter
    • 8.3.3. Serial to parallel converter
    • 8.3.4. Test for Parallel/Serial converters
  • 8.4. Random access memory (RAM)
    • 8.4.1. Single port RAM
    • 8.4.2. Visual test : single port RAM
    • 8.4.3. Dual port RAM
    • 8.4.4. Visual test : dual port RAM
  • 8.5. Read only memory (ROM)
    • 8.5.1. ROM implementation using RAM (block ROM)
    • 8.5.2. Visual test
  • 8.6. Queue with first-in first-out functionality
    • 8.6.1. Queue design
    • 8.6.2. Visual test
• 9. Testbenches
  • 9.1. Introduction
  • 9.2. Testbench for combinational circuits
    • 9.2.1. Half adder
  • 9.3. Testbench with ‘initial block’
    • 9.3.1. Read data from file
    • 9.3.2. Write data to file
  • 9.4. Testbench for sequential designs
  • 9.5. Conclusion
• 10. SystemVerilog for synthesis
  • 10.1. Introduction
  • 10.2. Verilog, VHDL and SystemVerilog
  • 10.3. ‘logic’ data type
  • 10.4. Specialized ‘always’ blocks
    • 10.4.1. ‘always_comb’
    • 10.4.2. ‘always_latch’
    • 10.4.3. ‘always_ff’
  • 10.5. User define types
    • 10.5.1. ‘typedef’
    • 10.5.2. ‘enum’
    • 10.5.3. Example
  • 10.6. Conclusion
• 11. Packages
  • 11.1. Introduction
  • 11.2. Creating packages
  • 11.3. Import package
  • 11.4. Package with conditional compilation
    • 11.4.1. Modify my_package.sv
    • 11.4.2. Testbench
• 12. Interface
  • 12.1. Introduction
  • 12.2. Define and use interface
• 13. Simulate and implement SoPC design
  • 13.1. Introduction
  • 13.2. Creating Quartus project
  • 13.3. Create custom peripherals
  • 13.4. Create and Generate SoPC using Qsys
  • 13.5. Create Nios system
  • 13.6. Add and Modify BSP
    • 13.6.1. Add BSP
    • 13.6.2. Modify BSP (required for using onchip memory)
  • 13.7. Create application using C/C++
  • 13.8. Simulate the Nios application
  • 13.9. Adding the top level Verilog design
  • 13.10. Load the Quartus design (i.e. .sof/.pof file)
  • 13.11. Load the Nios design (i.e. ‘.elf’ file)
  • 13.12. Saving NIOS-console’s data to file
  • 13.13. Conclusion
• 14. Reading data from peripherals
  • 14.1. Introduction
  • 14.2. Modify Qsys file
  • 14.3. Modify top level design in Quartus
  • 14.4. Modify Nios project
    • 14.4.1. Adding Nios project to workspace
  • 14.5. Add ‘C’ file for reading switches
  • 14.6. Simulation and Implementation
  • 14.7. Conclusion
• 15. UART, SDRAM and Python
  • 15.1. Introduction
  • 15.2. UART interface
  • 15.3. NIOS design
  • 15.4. Communication through UART
  • 15.5. SDRAM Interface
    • 15.5.1. Modify QSys
    • 15.5.2. Modify Top level Quartus design
    • 15.5.3. Updating NIOS design
  • 15.6. Live plotting the data
  • 15.7. Conclusion
• 16. Script execution in Quartus and Modelsim
  • 16.1. Quartus
    • 16.1.1. Generating the RTL view
    • 16.1.2. Loading design on FPGA board
  • 16.2. Modelsim
• 17. How to implement NIOS-designs
  • 17.1. Create project
  • 17.2. Add all files from VerilogCodes folder
  • 17.3. Generate and Add QSys system
  • 17.4. Nios system