Dataflow level D flip flop in Verilog

Dataflow level D flip flop in Verilog

//========================================
// Dataflow level D flip flop in Verilog
//========================================
`timescale 10ns/10ps 
module D_FF(D,CLK,Q,Qbar);
input D,CLK;
output Q,Qbar;

wire d1,d2,d3,d4,d5,d6,d7,d8;

assign d1= ~(D & d3);
assign d2= ~(d1 & d3);
assign d3= ~ CLK;

assign d4= ~(d8 & d1);
assign d8= ~(d2 & d4);

assign d5 = ~ d3;

assign d6= ~(d4 & d5);
assign d7= ~(d6 & d5);

assign Q= ~(d6 & Qbar);
assign Qbar= ~(Q & d7);

endmodule

//==========================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module D_FF(D,CLK,Q,Qbar);

input D,CLK;

output Q,Qbar;

*/

reg D,CLK= 1'b10;   //  暫存器資料初值為‘0’

wire Q,Qbar;

integer i;

D_FF  UUT (D,CLK,Q,Qbar);

initial begin

    for (i=0; i<5; i=i+1) begin

          D = i;

         #35;

    end

    #25

     $stop;

end

always

begin

#25

     CLK=~CLK;

end 

endmodule