2 bit square generator in Verilog

2 bit square generator in Verilog (2bit 平方產生器)

1)Gate Level 
//=============================
//gate level
module twobit_square(I,O);
input [1:0]I;
output [3:0]O;

// Declares gnd, and assigns it to 0
wire gnd = 1'b0;

wire w1;
not u1(w1,I[0]);
buf u2(O[0],I[0]);
buf u3(O[1],gnd);
and u4(O[2],w1,I[1]);
and u5(O[3],I[1],I[0]);

endmodule

//=============================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps   
module Test_bench;
/*
module twobit_square(I,O);
input [1:0]I;
output [3:0]O;
*/

// Inputs
reg [1:0]I=2'b00;
// Outputs
wire [3:0] O;
integer i;

// Instantiate the Unit Under Test (UUT)

twobit_square UUT (I,O);

initial begin
  $monitor (I,O);
  for(i=1; i<=7; i=i+1)
begin
#20 I = I+1;
end

end
endmodule

2)Dataflow Level 

//dataflow level 

module twobit_square(I,O);

input [1:0]I;

output [3:0]O;

// Declares gnd, and assigns it to 0

wire gnd = 1'b0;

assign O[0]=I[0];

assign O[1]=gnd;

assign O[2]=I[1] & ( ~I[0]);

assign O[3]=I[1] & I[0];

endmodule

3) Behavior if

//Behavior level  if

module twobit_square(I,O);

input [1:0]I;

output reg [3:0]O;

always @ (*)

begin

if (I==0) O=4'b0000;

else if (I==1) O=4'b0001;

else if (I==2) O=4'b0100;

else if (I==3) O=4'b1001;

end

endmodule

 4) Behavior case

//Behavior level  case

module twobit_square(I,O);

input [1:0]I;

output reg [3:0]O;

always @ (*) begin

case (I)

0 :  O=4'b0000;

1 :  O=4'b0001;

2 :  O=4'b0100;

3 :  O=4'b1001;

endcase

end

endmodule