1x4 DeMux with bitwise operator in Verilog

1x4 DeMux with bitwise operator in Verilog

//========================
//Dataflow demux 1x4
//========================
`timescale 10ns/10ps
module Demux_1x4(I,S,Y);
input I;
input [1:0]S;
output [3:0]Y;

assign Y[0]= I & (~S[1]) & (~S[0]) ;
assign Y[1]= I & (~S[1]) & ( S[0]) ;
assign Y[2]= I & ( S[1]) & (~S[0]) ;
assign Y[3]= I & ( S[1]) & ( S[0]) ;

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Demux_1x4(I,S,Y);

input I;

input [1:0]S;

output [3:0]Y;

*/

reg [1:0]S= 2'b00;   //  暫存器資料初值為‘00’

reg I=1'b0;

wire [3:0]Y;

integer i;

Demux_1x4 UUT (I,S,Y);

initial begin

    for (i=0; i<9; i=i+1) begin

         {I,S} = i;

         #20;

    end

    #20

     $stop;

end

endmodule