Verilog not , buf , bufif0 , bufif1 , notif0 , notif1

Verilog not , buf , bufif0 , bufif1 , notif0 , notif1

//=======================================
module not_buf(data_enable_low, in ,data_bus1,data_bus2,data_bus3,data_bus4, out1, out2 );  

input  data_enable_low, in;
output data_bus1,data_bus2,data_bus3,data_bus4, out1, out2;


bufif0 U1(data_bus1,in, data_enable_low);
bufif1 U2(data_bus2,in, data_enable_low);

notif0 U3(data_bus3,in, data_enable_low);
notif1 U4(data_bus4,in, data_enable_low);

buf  U5(out1,in);
not  U6(out2,in);

endmodule
//====================================

`timescale 100ns/10ps

module T; 

reg data_enable_low=1'b0;
reg in=1'b1;

wire data_bus1,data_bus2,data_bus3,data_bus4, out1, out2;

not_buf UUT(.data_enable_low(data_enable_low), .in(in) ,.data_bus1(data_bus1),.data_bus2(data_bus2),.data_bus3(data_bus3),.data_bus4(data_bus4),.out1(out1), .out2(out2) ); 

initial begin
  $monitor(
    "@%g in=%b data_enable_low=%b out1=%b out2= b data_bus1=%b  data_bus2=%b  data_bus3=%b data_bus4=%b" ,
    $time, in, data_enable_low, out1, out2, data_bus1, data_bus2, data_bus3, data_bus4);
   
  data_enable_low = 0;
  in = 1;
  #40 data_enable_low = 1;
  #60 data_enable_low = 0;
  #80 $finish;
end

always #20 in = ~in;


endmodule