Half Adder Behavioral Model using If-Else Statement in Verilog

Half Adder Behavioral Model using If-Else Statement in Verilog

源自於 https://electronicstopper.blogspot.com/2017/06/half-adder-behavioral-model-using-if.html

Code:

module halfadder4(input x, y, output reg s, c);

always@(x or y)
begin

if (x == 0 && y == 0)
begin
s = 0;
c = 0;
end

else if (x == 1 && y == 1)
begin
s = 0;
c = 1;
end

else
begin
s = 1;
c = 0;
end

end

endmodule

Testbench Code:

module half_adder_verilog_tb();

reg x, y;
wire s, c;

halfadder4 dut (.x(x), .y(y), .s(s), .c(c));

initial
begin

x = 1'b0;
y = 1'b0;
#50;

x = 1'b0;
y = 1'b1;
#50;

x = 1'b1;
y = 1'b0;
#50;

x = 1'b1;
y = 1'b1;

end

endmodule

Output: