同步與非同步Reset

同步與非同步Reset

源自於https://geekwentfreak-raviteja.rhcloud.com/2010/10/designing-asynchronous-and-synchronous-reset-in-verilog/

designing asynchronous and synchronous reset in verilog

Posted on October 7, 2010

Asynchronous reset doesn’t require the clock edge to reset the flip-flop whereas synchronous reset does. Let us design these in verilog and see how synthesis tools implements them.

Asynchronous Reset

dff_async_reset.v

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

module dff_async_reset( clk, reset, data, Q ); //input input clk, reset, data; //output output reg Q; always @(posedge clk, posedge reset) begin   if(reset) begin      Q <= 0;   end   else begin     Q <= data;   end end endmodule

FPGA provides asynchronous reset and set options for every register(D flip-flop). Hence, asynchronous resets are implemented by synthesis tools using this reset pin.

Synchronous Reset

dff_sync_reset.v

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

module dff_sync_reset( clk, reset, data, Q ); //input input clk, reset, data; //output output reg Q; //synchronous always @(posedge clk) begin   if(reset) begin     Q <= 0;   end   else begin     Q <= data;   end end endmodule

For synchronous reset, synthesis tool models the reset as another input, selecting either data signal or zero using a mux based on the reset signal.

Which to use

Though synchronous reset results in extra combination logic, it is more efficient because asynchronous reset suffers from metastable state. Metastability in asynchronous reset occurs when reset is de-asserted very close to clock edge and hence violates reset recovery time.