ASIC Digital Design (Verilog Examples)

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Verilog examples‎ > ‎Design components (building blocks)‎ > ‎ BCD up/down counter // ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ // ~ -- // ~ Published by: www.asic-digital-design.com // ~ -- // ~ Description: This is synchronous 4-bit BCD counter // ~ with possibility to count UP or DOWN. // ~ UP: dir='1' // ~ DOWN: dir='0' // ~ -- // ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ module cnt_bcddir ( dout4, dir, clk, arst, srst, en ); output [3:0] dout4; input dir; input clk, arst, srst, en; // declaration of signals inside this block reg [3:0] reg_cnt; reg [3:0] nxt_cnt; always @ ( posedge arst or posedge clk ) // dff_cnt begin if ((arst == 1'b1)) reg_cnt <= 1'h0; else if ((srst == 1'b1)) reg_cnt <= 1'h0; else if ((en == 1'b1)) reg_cnt <= nxt_cnt; end // end dff_cnt always @ ( reg_cnt or dir ) // cmb_cnt begin if ((dir == 1'b0)) if ((reg_cnt == 9)) nxt_cnt <= 1'h0; else nxt_cnt <= (reg_cnt + 1); else if ((reg_cnt == 0)) nxt_cnt <= 4'b1001; else nxt_cnt <= (reg_cnt - 1); end // end cmb_cnt // outputs -- assign {dout4}=reg_cnt; //-- endmodule See Warranty Disclaimer before information at this page is used. Any comments are welcome at e-mail. 註解 您沒有加入註解的權限。

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