QUARTUS II FSM state Machine

QUARTUS II FSM state Machine 
1)new File

2) State Tools

3). Insert  Input Port  / Insert Output Port  -> and Rename Input / Output X ,Qout

4). Transition Tool

5). State Table

6). State Machine Wizard

Reset Active change to Low

page of [ 2 od 4]   Edit Transition 

Action Page of [3 of 4] 

7) Generate HDL File

8) 選擇Verilog file

9)


// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// Generated by Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
// Created on Wed Nov 14 10:24:28 2012

// synthesis message_off 10175

`timescale 1ns/1ns

module MOORE_ex2 (
    reset,clock,X,
    Qout);

    input reset;
    input clock;
    input X;
    tri0 reset;
    tri0 X;
    output Qout;
    reg Qout;
    reg [3:0] fstate;
    reg [3:0] reg_fstate;
    parameter S0=0,S1=1,S2=2,S3=3;

    always @(posedge clock)
    begin
        if (clock) begin
            fstate <= reg_fstate;
        end
    end

    always @(fstate or reset or X)
    begin
        if (~reset) begin
            reg_fstate <= S0;
            Qout <= 1'b0;
        end
        else begin
            Qout <= 1'b0;
            case (fstate)
                S0: begin
                    if (~(X))
                        reg_fstate <= S0;
                    else if (X)
                        reg_fstate <= S2;
                    // Inserting 'else' block to prevent latch inference
                    else
                        reg_fstate <= S0;

                    Qout <= 1'b0;
                end
                S1: begin
                    if (~(X))
                        reg_fstate <= S0;
                    else if (X)
                        reg_fstate <= S2;
                    // Inserting 'else' block to prevent latch inference
                    else
                        reg_fstate <= S1;

                    Qout <= 1'b1;
                end
                S2: begin
                    if (X)
                        reg_fstate <= S3;
                    else if (~(X))
                        reg_fstate <= S2;
                    // Inserting 'else' block to prevent latch inference
                    else
                        reg_fstate <= S2;

                    Qout <= 1'b1;
                end
                S3: begin
                    if (X)
                        reg_fstate <= S1;
                    else if (~(X))
                        reg_fstate <= S3;
                    // Inserting 'else' block to prevent latch inference
                    else
                        reg_fstate <= S3;

                    Qout <= 1'b0;
                end
                default: begin
                    Qout <= 1'bx;
                    $display ("Reach undefined state");
                end
            endcase
        end
    end
endmodule // MOORE_ex2