源自於
http://www.lbebooks.com/downloads/exportal/Verilog_BASYS_Example62-TrafficLights.pdf
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// Example 62: traffic_lights_top
module traffic_light_top (LEDR, LEDG , CLOCK_50 ,KEY );
input [3:0] KEY; // Push bottom
input CLOCK_50; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
// (
//input wire clk ,
//input wire [3:3] btn ,
//output wire [7:2] ld
//);
wire [5:0] ld;
wire clk3;
wire clr;
assign clr = KEY[0]; //reset KEY
clkdiv U1 (.clk(CLOCK_50), //50MHZ
.clr(clr),
.clk3(clk3)
);
traffic U2 (.clk(clk3),
.clr(clr),
.lights(ld)
);
assign LEDR[17]=clk3;
assign LEDR[2:0]=ld[2:0];
assign LEDG[2:0]=ld[5:3];
endmodule
// Example 62b: clock divider
module clkdiv (
input wire clk ,
input wire clr ,
output wire clk3
);
reg [24:0] q;
// 25-bit counter
always @(posedge clk or negedge clr) //DE2-70 is Low active
begin
if (!clr == 1)
q <= 0;
else
q <= q + 1;
end
assign clk3 = q[24]; // 3 Hz
endmodule
// Example 62a: traffic lights
module traffic (
input wire clk ,
input wire clr ,
output reg [5:0] lights
);
reg [2:0] state;
reg [3:0] count;
parameter S0 = 3'b000, S1 =3'b001, S2 = 3'b010, // states
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
parameter SEC5 = 4'b1111, SEC1 = 4'b0011; // delays
always @(posedge clk or negedge clr)
begin
if (!clr == 1)
begin
state <= S0;
count <= 0;
end
else
case (state)
S0: if (count < SEC5)
begin
state <= S0;
count <= count + 1;
end
else
begin
state <= S1;
count <= 0;
end
S1: if (count < SEC1)
begin
state <= S1;
count <= count + 1;
end
else
begin
state <= S2;
count <= 0;
end
S2: if (count < SEC1)
begin
state <= S2;
count <= count + 1;
end
else
begin
state <= S3;
count <= 0;
end
S3: if (count < SEC5)
begin
state <= S3;
count <= count + 1;
end
else
begin
state <= S4;
count <= 0;
end
S4: if (count < SEC1)
begin
state <= S4;
count <= count + 1;
end
else
begin
state <= S5;
count <= 0;
end
S5: if (count < SEC1)
begin
state <= S5;
count <= count + 1;
end
else
begin
state <= S0;
count <= 0;
end
default state <= S0;
endcase
end
always @(*)
begin
case (state)
S0: lights = 6'b100001;
S1: lights = 6'b100010;
S2: lights = 6'b100100;
S3: lights = 6'b001100;
S4: lights = 6'b010100;
S5: lights = 6'b100100;
default lights = 6'b100001;
endcase
end
endmodule
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