P6-79 16x8 bits 2 Port RAM 適用於DE2-70

P6-79 16x8bits 2 Port RAM 適用於DE2-70
因為Clock 50MHz 太快了 所以將Clock 速度Down 下來

reg [27:0] Counter_inc ;

reg [3:0] key_delay0;





 always @ (posedge CLOCK_50 ) 
key_delay0 <= { key_delay0[2:0],Counter_inc[25]};   //delay for KEY[0]

Counter_inc = Counter_inc + 28'b1;

pin assignment

assign ADDR = SW[3:0] ; //1'st port address 

assign DPR_ADDR=SW[7:4] ; //2'nd port address

assign di=SW[15:8];     //Data input 

assign we=SW[17];       //Wire Enable

assign LEDG[7:0] = SP_OUT; //1'st data output 

assign LEDR[7:0] = DP_OUT; //2'nd data output 

寫入動作順序 

                  (1) Setting Address SW[3:0]  第一組Address 或是  SW[7:4] 第二組Address

                  (2) Setting Data  SW[15:8]    設定Data

                  (3) Setting Writing Enable SW[17]  寫入致能

                  (4) 等   if (!key_delay0[3] && key_delay0[2] && we )         

讀出動作順序 

                  (1) Setting Address SW[3:0]  第一組Address 或是  SW[7:4] 第二組Address
                  (2) 等   if (!key_delay0[3] && key_delay0[2] && we )           

  

//Filename : RAM16x8d.V
//-------------------------------------
//Inferring a 16x8 Dual Port Block Ram 
//File name : RAM16x8d.v
//-------------------------------------
module RAM16x8d (LEDG, LEDR, CLOCK_50, KEY , SW);
parameter Length =4;
output [7:0] LEDG;
output [17:0] LEDR;
input  CLOCK_50 ;
input  [3:0] KEY;
input  [17:0] SW;

//(clk, we, ADDR, DPR_ADDR, di, SP_OUT, DP_OUT);
parameter DATA_WDTH = 8, ADDR_WDTH = 4;
wire we; //Write Enable
wire [ADDR_WDTH-1:0] ADDR;     //1'st port address  
wire [ADDR_WDTH-1:0] DPR_ADDR; //2'nd port address
wire [DATA_WDTH-1:0] di;       //Data input 
reg  [DATA_WDTH-1:0] SP_OUT;   //1'st data output 
reg  [DATA_WDTH-1:0] DP_OUT;   //2'nd data output 

// 16-byte ram 
reg    [DATA_WDTH-1:0] ram [15:0];  //16x8 Bits ,Address bus= 2^4 ,4bits
//Data bits =8
reg [3:0] key_delay0;    //For Clock Down to 26bits 
reg [27:0] Counter_inc ;

assign ADDR = SW[3:0] ; //1'st port address 
assign DPR_ADDR=SW[7:4] ; //2'nd port address

assign di=SW[15:8];     //Data input 
assign we=SW[17];



always @ (posedge CLOCK_50 ) begin

if (!key_delay0[3] && key_delay0[2] && we ) //KEY[0] = Counter_inc[25]
ram[ADDR] <= di; 

key_delay0 <= { key_delay0[2:0],Counter_inc[25]};   //delay for KEY[0]

Counter_inc = Counter_inc + 28'b1;

SP_OUT <= ram[ADDR]; 
DP_OUT <= ram[DPR_ADDR]; 

end

assign LEDG[7:0] = SP_OUT; //1'st data output 
assign LEDR[7:0] = DP_OUT; //2'nd data output 

endmodule







/*
//-------------------------------------
//Inferring a 16x8 Dual Port Block Ram 
//File name : RAM16x8d.v
//-------------------------------------
module RAM16x8d(clk, we, ADDR, DPR_ADDR, di, SP_OUT, DP_OUT);
 parameter DATA_WDTH = 8, ADDR_WDTH = 4;
 input  clk; 
 input  we; 
 input  [ADDR_WDTH-1:0] ADDR;     //1'st port address  
 input  [ADDR_WDTH-1:0] DPR_ADDR; //2'nd port address
 input  [DATA_WDTH-1:0] di;       //Data input 
 output [DATA_WDTH-1:0] SP_OUT;   //1'st data output 
 output [DATA_WDTH-1:0] DP_OUT;   //2'nd data output 

 // 16-byte ram
 reg    [DATA_WDTH-1:0] ram [15:0]; 

 always @(posedge clk) begin 
  if (we) 
  ram[ADDR] <= di; 
 end 

 assign SP_OUT = ram[ADDR]; 
 assign DP_OUT = ram[DPR_ADDR]; 

endmodule

*/