P6-10 4 Bit Register （BLOCKING）區塊指定

P6-10 4 Bit Register （BLOCKING）區塊指定 適用於DE2-70



assign RESET = KEY[0];
assign Din1 = SW[0];
assign Din2 = SW[1];
assign CLK1 = KEY[1];   //Enable 



4bit 都是0 或1  1個CLOCK 出現時 同時0或1


   Qout[0] = Din;
   Qout[1] = Qout[0];
   Qout[2] = Qout[1];
   Qout[3] = Qout[2];
//自動執行 Clock 50MHZ trig Event
//手動執行 KEY[1] trig Event


//--------------------------------------------------
//4-bit register for Blocking Procedural Assignment
//Filename : reg_bpa.v
//--------------------------------------------------
module reg4_Block(LEDG, LEDR, CLOCK_50, KEY , SW);

output [7:0] LEDG;
output [17:0] LEDR;
input  CLOCK_50 ;
input  [3:0] KEY;
input  [17:0] SW;

wire RESET , Din1, Din2 ;
reg [3:0 ] Qout;
reg [3:0 ] Q1out;


reg [3:0] key_delay0;
reg [3:0] key_delay1;
reg [27:0] Counter_inc ;

assign RESET = KEY[0];
assign Din1 = SW[0];
assign Din2 = SW[1];

    
assign CLK1 = KEY[1];

assign LEDR[3:0] = Qout;
        assign LEDG[3:0] = Q1out;
    
    
    
always @ (posedge CLOCK_50 )
begin
//Positive edge CLK and asynchronous RESET
if (!RESET)

 Qout = 4'b0000;
else if (!key_delay0[3] && key_delay0[2]) //KEY[0] = Counter_inc[27]
begin
Qout[0] = Din2;
Qout[1] = Qout[0];
Qout[2] = Qout[1];
Qout[3] = Qout[2];
end

key_delay0 <= { key_delay0[2:0],Counter_inc[27]};   //delay for KEY[0]

Counter_inc = Counter_inc + 28'b1;

end


//============================================================
  
always @ (posedge CLOCK_50  )
begin
//Negitive edge CLK1 and asynchronous RESET
if (!RESET)

 Q1out = 4'b0000;
else if (!key_delay1[3] && key_delay1[2]) //KEY[1] 
begin
Q1out[0] = Din1;
Q1out[1] = Q1out[0];
Q1out[2] = Q1out[1];
Q1out[3] = Q1out[2];
end

key_delay1 <= { key_delay1[2:0],CLK1};   //delay for KEY[1]

end


endmodule


/*
//--------------------------------------------------
//4-bit register for Blocking Procedural Assignment
//Filename : reg_bpa.v
//--------------------------------------------------
module reg4_bpa(Qout, CLK, RESET, Din);
output [3:0] Qout;
input CLK, RESET;
input Din;

reg [3:0] Qout;


always @ (posedge CLK or posedge RESET)
//Positive edge CLK and asynchronous RESET
 if (RESET)
   Qout = 4'b0000;
 else
  begin
   Qout[0] = Din;
   Qout[1] = Qout[0];
   Qout[2] = Qout[1];
   Qout[3] = Qout[2];
  end
endmodule
*/