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2020年1月4日星期六

Verilog 4Bits Adder gate level

源自於 http://ccckmit.wikidot.com/ve:adder4

module fulladder (input a, b, c_in, output sum, c_out);
wire s1, c1, c2;

xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module Adder_4bit(input signed [3:0] a, input signed [3:0] b, input c_in, output signed [3:0] sum, output c_out);
wire [3:0] c;

fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ;
fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ;
fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ;
fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ;

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps

module Test_bench;
reg [3:0] a;
reg [3:0] b;
reg c_in;

wire [3:0] sum;
wire c_out;

//module Adder_4bit (input a, b, c_in, output sum, c_out);
Adder_4bit UUT(
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
a = 4'h0;
b = 4'h0;
c_in = 4'h0;
$monitor(a,b,c_in,sum,c_out);
#160; c_in = 4'h1;
end

always #20 a = a + 3;
always #40 b = a + 2;

initial begin
#320 $finish();
end
endmodule

verilog 74LS83 4bit Adder

module adder_74ls83(A, B, C0 ,S,C4);
output [3:0] S;
output C4;
input [3:0] A;
input [3:0] B;
input C0;

assign #10 {C4,S} = A + B + C0;

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

reg [3:0] A;

reg [3:0] B;

reg C0;

wire [3:0] S;

wire C4;

adder_74ls83 UUT(

.A(A),

.B(B),

.C0(C0),

.S(S),

.C4(C4)

);

initial begin

A = 4'h0;

B = 4'h0;

C0 = 4'h0;

$monitor(A,B,C0,S,C4);

#160; C0 = 4'h1;

end

always #20 A = A + 3;

always #40 B = A + 2;

initial begin

#320 $finish();

end

endmodule

Verilog 4Bits Adder gate level

Verilog 4Bits Adder gate level

源自於
https://www.cnblogs.com/oomusou/archive/2008/07/11/verilog_4_bit_full_adder.html

module Adder_4bit_gatelevel(
input [3:0] a,
input [3:0] b,
input ci,
output [3:0] s,
output co
);

wire [2:0] carry;

function fa_s(input a, input b, input ci);
fa_s = a ^ b ^ ci;
endfunction

function fa_co(input a, input b, input ci);
fa_co = a & ci | a & b | b & ci;
endfunction

assign s[0] = fa_s (a[0], b[0], ci);
assign carry[0] = fa_co(a[0], b[0], ci);

assign s[1] = fa_s (a[1], b[1], carry[0]);
assign carry[1] = fa_co(a[1], b[1], carry[0]);

assign s[2] = fa_s (a[2], b[2], carry[1]);
assign carry[2] = fa_co(a[2], b[2], carry[1]);

assign s[3] = fa_s (a[3], b[3], carry[2]);
assign co = fa_co(a[3], b[3], carry[2]);

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg [3:0] a;
reg [3:0] b;
reg ci;

wire [3:0] s;
wire co;

Adder_4bit_gatelevel UUT(
.a(a),
.b(b),
.ci(ci),
.s(s),
.co(co)
);

initial begin
a = 4'h0;
b = 4'h0;
ci = 4'h0;
$monitor(a,b,ci,s,co);
#160; ci = 4'h1;
end

always #20 a = a + 1;
always #40 b = a + 2;

initial begin
#320 $finish();
end
endmodule

2020年1月3日星期五

8 bits Counters and their use in clock dividers

8 bits Counters and their use in clock dividers

https://www.realdigital.org/doc/9c21eab4a0f85c50486858a87380d1f6

module Clock_Dividers(
input clk, rst,
output reg [7:0] counterout
);

always @ (posedge(clk), posedge(rst))
begin
if (rst) counterout <= 0;
else counterout <= counterout + 1;
end
endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

// Inputs

reg clk ; //輸入的訊號

reg rst ; //rst=1 , 0開始count

// Outputs

wire [7:0] counterout; //除過的訊號輸出

// Instantiate the Unit Under Test (UUT)

//module Clock_Dividers(

// input clk, rst,

// output reg [7:0] counterout

Clock_Dividers UUT (

.clk(clk), //輸入的訊號

.rst(rst), //reset, 0開始count

.counterout(counterout) //除過的訊號輸出

);

initial begin

$monitor(clk,rst,counterout);

// Initialize Inputs

clk <= 1'b0;

rst <= 1'b0;

#4000 $finish();

end

always #10 clk=~clk;

endmodule

Clock Dividers Counters and their use in clock dividers

Clock Dividers Counters and their use in clock dividers

module MOD_10(
clk_in, //輸入的訊號
cnt_enb,//count enable, 0開始count
ck_out //除過的訊號輸出
);

input clk_in;
input cnt_enb;
output ck_out;

reg ck_out;

//internal var
reg [7:0] cnt; //計數暫存器，最多255

always @(posedge clk_in) //正緣觸發
begin
if(!cnt_enb) //還沒開始，歸0
begin
cnt <= 0;
ck_out <= 0;
end
else //開始計數
begin
if(cnt >= 5) //修改這裡可以決定除頻值
begin
cnt <= 0; //重新計算
ck_out <= ~ck_out; //原本的波形取反向
end
else
begin
cnt <= cnt+1; //計數
end
end
end
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;

// Inputs
reg clk_in; //輸入的訊號
reg cnt_enb;//count enable, 0開始count

// Outputs
wire ck_out; //除過的訊號輸出

// Instantiate the Unit Under Test (UUT)
//module MOD_10(
// clk_in, 輸入的訊號
//cnt_enb,//count enable, 0開始count
//ck_out //除過的訊號輸出 );

MOD_10 UUT (
.clk_in(clk_in), //輸入的訊號
.cnt_enb(cnt_enb),//count enable, 0開始count
.ck_out(ck_out) //除過的訊號輸出
);

initial begin
$monitor(clk_in,cnt_enb,ck_out);
// Initialize Inputs
clk_in <= 1'b1;
cnt_enb<= 1'b1;
#400 $finish();
end

always #10 clk_in=~clk_in;

endmodule

https://www.fpga4student.com

https://www.fpga4student.com

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https://www.fpga4student.com/2017/08/verilog-code-for-clock-divider-on-fpga.html

Master Slave JK Flip Flop Verilog Code

Master Slave JK Flip Flop Verilog Code

module MasterSlave_JK_Flip_Flop(j,k,reset,clk,q,qbar);
input j,k,clk,reset;
output q,qbar;
Master M1(j,k,reset,clk,qx,qbarx);
Master S2(qx,qbarx,reset,!clk,q,qbar);
endmodule

//===========================
module Master(j,k,reset,clk,q,qbar);
input j,k,reset,clk;
output reg q,qbar;
initial
q = 0;
always @(posedge clk)begin
if(~reset)begin
case ({j,k})
2'b00:begin
q = q;
qbar = qbar;
end
2'b01:begin
q = 1'b0;
qbar =1'b1;
end
2'b10:begin
q = 1'b1;
qbar =1'b0;
end
2'b11:begin
q = ~ q;
qbar =~qbar;
end
endcase
end
else begin
q <= 1'bz;
qbar <= 1'bz;
end
end
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;

// Inputs
reg clk=1,reset=0,j=1,k=0;

// Outputs
wire q,qbar;

// Instantiate the Unit Under Test (UUT)
//MasterSlave_JK_Flip_Flop(j,k,reset,clk,q,qbar);
MasterSlave_JK_Flip_Flop UUT(
.j(j),
.k(k),
.reset(reset),
.clk(clk),
.q(q),
.qbar(qbar) );

initial begin
$monitor(j,k,reset,clk,q,qbar);
// Initialize Inputs
#25 j=1;k=1;
#25 j=1;k=0;
#25 j=1;k=1;
#25 j=0;k=1;
#25 j=1;k=1;
#25 j=0;k=0;
#25 j=1;k=1;
#25 j=1;k=0;
#25 j=1;k=1;
reset=1;
#25 j=1;k=0;
#25 j=1;k=1;
#25 j=0;k=1;
reset=0;
#25 j=1;k=1;
#25 j=0;k=0;
#25 j=1;k=1;
#25 j=1;k=0;

end

always #10 clk<=~clk;

initial begin
#440; // 模擬終止時間 440 ns
$stop;
end

endmodule

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2020年1月4日 星期六

2020年1月3日 星期五

2020年1月4日星期六

2020年1月3日星期五