HDLBits/Building Larger Circuits/Enable shift register（Exams/review2015 fsmshift）

 HDLBits/Building Larger Circuits/Enable shift register（Exams/review2015 fsmshift）

This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).

狀態機定義幾個狀態，然後當reset信號有效，進入狀態S0，reset信號消失就進入S1，然後進入S2、S3、S4，當進入S4狀態，下一個狀態就永遠保持為S4。然後shift_ena信號在狀態S0、S1、S2、S3時有效，這樣就完成了題目。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
    reg [2:0] state;
    reg [2:0] next_state;
    
    always@(posedge clk)begin
        if(reset)begin
            state <= S0;
        end
        else begin
            state <= next_state;
        end
    end
    
    always@(*)begin
        case(state)
            S0:begin
                next_state = S1;
            end
            S1:begin
                next_state = S2;
            end
            S2:begin
                next_state = S3;
            end
            S3:begin
                next_state = S4;
            end
            S4:begin
                next_state = S4;
            end
            default:begin
                next_state = S4;
            end
        endcase
    end
    
    assign shift_ena = (state == S0 || state == S1 || state == S2 || state == S3);
 endmodule