HDLBits/Sequential Logic/Finite State Machines/Fsm onehot

HDLBits/Sequential Logic/Finite State Machines/Fsm onehot 

Given the following state machine with 1 input and 2 outputs:

Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.

Implement the state transition logic and output logic portions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);

    parameter s0=10'b00_0000_0001;
    parameter s1=10'b00_0000_0010;
    parameter s2=10'b00_0000_0100;
    parameter s3=10'b00_0000_1000;
    parameter s4=10'b00_0001_0000;
    parameter s5=10'b00_0010_0000;
    parameter s6=10'b00_0100_0000;
    parameter s7=10'b00_1000_0000;
    parameter s8=10'b01_0000_0000;
    parameter s9=10'b10_0000_0000;


    always@(*)begin
        case(state)
            s0:next_state = in ? s1:s0;
            s1:next_state = in ? s2:s0;
            s2:next_state = in ? s3:s0;
            s3:next_state = in ? s4:s0;
            s4:next_state = in ? s5:s0;
            s5:next_state = in ? s6:s8;
            s6:next_state = in ? s7:s9;
            s7:next_state = in ? s7:s0;
            s8:next_state = in ? s1:s0;
            s9:next_state = in ? s1:s0;
            default:
                next_state = s0;
        endcase 
    end

    //输出
    assign out1 = state==s8||state==s9;
    assign out2 = state==s7||state==s9;

endmodule

官方解答?????

module top_module(

    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);

    assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]);
    assign next_state[1] = in & (state[0] | state[8] | state[9]);
    assign next_state[2] = in & state[1];
    assign next_state[3] = in & state[2];
    assign next_state[4] = in & state[3];
    assign next_state[5] = in & state[4];
    assign next_state[6] = in & state[5];
    assign next_state[7] = in & (state[6] | state[7]);
    assign next_state[8] = ~in & state[5];
    assign next_state[9] = ~in & state[6];

    assign out1 = state[8] | state[9];
    assign out2 = state[7] | state[9];

endmodule